Graphics processor with arithmetic and elementary function units

Abstract

A graphics processor capable of efficiently performing arithmetic operations and computing elementary functions is described. The graphics processor has at least one arithmetic logic unit (ALU) that can perform arithmetic operations and at least one elementary function unit that can compute elementary functions. The ALU(s) and elementary function unit(s) may be arranged such that they can operate in parallel to improve throughput. The graphics processor may also include fewer elementary function units than ALUs, e.g., four ALUs and a single elementary function unit. The four ALUs may perform an arithmetic operation on (1) four components of an attribute for one pixel or (2) one component of an attribute for four pixels. The single elementary function unit may operate on one component of one pixel at a time. The use of a single elementary function unit may reduce cost while still providing good performance.

What is claimed is: 
     
         1 . An apparatus comprising:
 at least one arithmetic logic unit (ALU) operative to perform arithmetic operations; and   at least one elementary function unit operative to compute elementary functions, wherein the at least one elementary function unit and the at least one ALU are operable on multiple threads in parallel.   
     
     
         2 . The apparatus of  claim 1 , wherein the at least one ALU comprises at least four ALUs. 
     
     
         3 . The apparatus of  claim 2 , wherein the at least four ALUs are configured to perform an arithmetic operation on up to four components of an attribute for a pixel. 
     
     
         4 . The apparatus of  claim 2 , wherein the at least four ALUs are configured to perform an arithmetic operation on a component of an attribute for up to four pixels. 
     
     
         5 . The apparatus of  claim 1 , wherein the at least one ALU comprises more than one ALU, and wherein the at least one elementary function unit comprises fewer elementary function units than ALUs. 
     
     
         6 . The apparatus of  claim 1 , wherein the at least one elementary function unit comprises a single elementary function unit. 
     
     
         7 . The apparatus of  claim 1 , wherein instructions for the at least one elementary function unit are compiled with synchronization as load instructions. 
     
     
         8 . The apparatus of  claim 1 , wherein control bits are used for synchronization of instructions for the at least one elementary function unit with other instructions dependent on the instructions for the at least one elementary function unit. 
     
     
         9 . The apparatus of  claim 1 , wherein the at least one ALU is configured to execute a first instruction for a first thread and the at least one elementary function unit is configured to execute a second instruction for a second thread in parallel with the at least one ALU. 
     
     
         10 . The apparatus of  claim 1 , wherein the at least one ALU and the at least one elementary function unit have different latency. 
     
     
         11 . The apparatus of  claim 1 , further comprising:
 a load control unit configured to facilitate exchanges of data between the at least one ALU and a memory system and between the at least one elementary function unit and the memory system.   
     
     
         12 . The apparatus of  claim 11 , wherein the at least one elementary function unit is coupled to the load control unit. 
     
     
         13 . The apparatus of  claim 12 , wherein the at least one elementary function unit is operable in parallel with the load control unit. 
     
     
         14 . The apparatus of  claim 12 , wherein requests for the at least one elementary function unit and load requests for the load control unit share a bus, and wherein the at least one elementary function unit and the load control unit are configured to execute different threads in parallel. 
     
     
         15 . The apparatus of  claim 1 , further comprising:
 a scheduler configured to receive threads from at least one graphics application and to schedule execution of the threads by the at least one ALU and the at least one elementary function unit.   
     
     
         16 . The apparatus of  claim 15 , wherein the at least one elementary function unit is coupled to the scheduler. 
     
     
         17 . The apparatus of  claim 1 , further comprising:
 an output buffer coupled to the at least one ALU and the at least one elementary function unit and operative to store results from the at least one ALU and the at least one elementary function unit.   
     
     
         18 . An integrated circuit comprising:
 at least one arithmetic logic unit (ALU) configured to perform arithmetic operations; and   at least one elementary function unit configured to compute elementary functions, wherein the at least one elementary function unit and the at least one ALU are operable on multiple threads in parallel.   
     
     
         19 . The integrated circuit of  claim 18 , wherein the at least one ALU comprises at least four ALUs and fewer than four elementary function units. 
     
     
         20 . A wireless device comprising:
 a graphics processor comprising at least one arithmetic logic unit (ALU) configured to perform arithmetic operations and at least one elementary function unit configured to compute elementary functions, wherein the at least one elementary function unit and the at least one ALU are operable on multiple threads in parallel; and   a memory system configured to store data for the graphics processor.   
     
     
         21 . The wireless device of  claim 20 , wherein the graphics processor comprises at least four ALUs and fewer than four elementary function units. 
     
     
         22 . An apparatus comprising:
 at least one arithmetic logic unit (ALU) operative to perform arithmetic operations; and   at least one elementary function unit operative to compute elementary functions, wherein the number of the at least one elementary function unit is fewer than the number of the at least one ALU.   
     
     
         23 . The apparatus of  claim 22 , wherein the at least one ALU is operable in parallel with the at least one elementary function unit. 
     
     
         24 . The apparatus of  claim 22 , further comprising:
 a load control unit configured to facilitate exchanges of data between the at least one ALU and a memory system and between the at least one elementary function unit and the memory system.   
     
     
         25 . The apparatus of  claim 24 , wherein the at least one elementary function unit is coupled to the load control unit.