Semiconductor device

Abstract

A semiconductor device according to this invention includes a first power line that supplies power to a first circuit, a second power line that supplies power to a second circuit, and a capacitive element that is provided between the first power line and the second power line.

1 . A semiconductor device comprising:
 a first power line supplying a first voltage to a first circuit;   a second power line supplying a second voltage to a second circuit, wherein the second circuit includes an input that receives a signal from the first circuit; and   a first capacitive element having a first terminal coupled to the first power line and a second terminal coupled to the second power line;   wherein the first and second voltages are operating voltages for the first and second circuits, respectively.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the second circuit is an output circuit that outputs a data signal to an output terminal of the semiconductor device. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the first circuit is a pre-stage circuit that is configured to output the signal to the second circuit, the signal being the result of one or more logic operations. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the first and second voltages are substantially equal. 
     
     
         5 . The semiconductor device of  claim 1 , comprising:
 a third power line supplying a third voltage to the first circuit; and   a fourth power line supplying a fourth voltage to the second circuit;   wherein the third and fourth voltages are ground potentials supplied to the first and second circuits by the third and fourth power lines, respectively.   
     
     
         6 . The semiconductor device of  claim 5 , wherein the third and fourth voltages are different from one another. 
     
     
         7 . The semiconductor device of  claim 5 , wherein:
 the first power line and the third power line form a first line coupling the first circuit to first and second terminals by which the first voltage and the third voltage are supplied, respectively; and   the second power line and the fourth power line form a second line coupling the second circuit to third and fourth terminals by which the second voltage and the fourth voltage are supplied, respectively.   
     
     
         8 . The semiconductor device of  claim 7 , comprising a second capacitive element having a first terminal coupled to the first line and a second terminal coupled to the second line. 
     
     
         9 . The semiconductor device of  claim 8 , wherein the second capacitive element is coupled to different power lines than that of the first capacitive element 
     
     
         10 . The semiconductor device of  claim 7 , comprising a second capacitive element having a first terminal coupled to the first power line and a second terminal coupled to the third power line. 
     
     
         11 . The semiconductor device of  claim 10 , comprising a third capacitive element having a first terminal coupled to the second power line and a second terminal coupled to the fourth power line. 
     
     
         12 . The semiconductor device of  claim 7 , comprising a second capacitive element having a first terminal coupled to the second power line and a second terminal coupled to the fourth power line. 
     
     
         13 . The semiconductor device of  claim 7 , comprising a second capacitive element having a first terminal coupled to the first power line and a second terminal coupled to the fourth power line. 
     
     
         14 . The semiconductor device of  claim 7 , comprising a second capacitive element having a first terminal coupled to the second power line and a second terminal coupled to the third power line. 
     
     
         15 . A semiconductor device comprising:
 a chip including a first circuit, a second circuit that receives an output of the first circuit, a first power line supplying a first operating voltage to the first circuit, a second power line supplying a second operating voltage to the second circuit, and a first capacitive element connected between the first and second power lines;   a printed circuit board comprising a first terminal and a second terminal, the first terminal being configured to provide the first operating voltage to the first power line and the second terminal being configured to provide the second operating voltage to the second power line; and   a package that connects the printed circuit board to the chip.   
     
     
         16 . The semiconductor device of  claim 15 , wherein the chip includes a first ground line supplying a first ground potential to the first circuit and a second ground line supplying a second ground potential to the second circuit. 
     
     
         17 . The semiconductor device of  claim 16 , wherein the printed circuit board comprises a third terminal and a fourth terminal, the third terminal being configured to provide the first ground potential to the first ground line and the fourth terminal being configured to provide the second ground potential to the second ground line. 
     
     
         18 . The semiconductor device of  claim 17 , wherein the printed circuit board comprises a fifth terminal configured to receive a data signal of the second circuit. 
     
     
         19 . The semiconductor device of  claim 15 , wherein the chip includes a large-scale integration (LSI) chip and the package includes an LSI package. 
     
     
         20 . The semiconductor device of  claim 16 , wherein the chip comprises a second capacitive element connected between one of either the first or second power lines and one of the first or second ground lines.