US2015021689A1PendingUtilityA1
Asymmetrical replacement metal gate field effect transistor
Est. expiryJul 18, 2033(~7 yrs left)· nominal 20-yr term from priority
H10P 30/222H10D 64/691H10D 64/667H10D 64/021H10D 64/015H10D 30/62H10D 64/017H10D 30/608H10D 30/603H10D 30/0275H10D 30/0227H10D 30/0221H10D 30/021H10D 64/251H10D 62/60H10D 30/022H01L 29/7835
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Claims
Abstract
An asymmetrical field effect transistor (FET) device includes a semiconductor substrate, a buried oxide layer disposed on the semiconductor substrate, an extended source region disposed on the buried oxide layer and a drain region disposed on the buried oxide layer. The asymmetrical FET device also includes a silicon on insulator region disposed between the extended source region and the drain region and a gate region disposed above the extended source region and the silicon on insulator region.
Claims
exact text as granted — not AI-modified1 . An asymmetrical field effect transistor (FET) device comprising:
a semiconductor substrate; a buried oxide layer disposed on the semiconductor substrate; an extended source region disposed on the buried oxide layer; a drain region disposed on the buried oxide layer; a silicon on insulator region disposed between the extended source region and the drain region; a gate region disposed above the extended source region and the silicon on insulator region, wherein the gate region overlaps a portion of the extended source region and wherein the drain region is not overlapped by the gate region.
2 . The asymmetrical FET device of claim 1 , further comprising a high-k layer disposed above the silicon on insulator region, the extended source region and the drain region.
3 . The asymmetrical FET device of claim 2 , further comprising a metal gate layer disposed between the high-k layer and a contact metal layer.
4 . The asymmetrical FET device of claim 1 , wherein a width of the extended source region is greater than a width of the drain region.
5 . The asymmetrical FET device of claim 1 , further comprising one or more spacers adjacent to a side portion of the gate region.
6 . (canceled)
7 . The asymmetrical FET device of claim 1 , wherein the asymmetrical FET device is a planar FET.
8 .- 20 . (canceled)Join the waitlist — get patent alerts
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