Nonvolatile semiconductor memory device and method of manufacturing the same

Abstract

According to one embodiment, a nonvolatile semiconductor memory device includes a first memory cell on the first fin-type active area, and a second memory cell on the second fin-type active area. Each of widths of charge storage layers of the first and second memory cells becomes narrower upward from below. Each of inter-electrode insulating layers of the first and second memory cells has a contact portion through which both are in contact with each other.

1 . (canceled) 
     
     
         2 . A nonvolatile semiconductor memory device comprising:
 a semiconductor substrate;   first and second active areas adjacent to each other in a first direction on the semiconductor substrate;   a first memory cell on the first active area, the first memory cell including a first gate insulating layer on the first active area, a first charge storage layer on the first gate insulating layer and in which a first width thereof in the first direction becomes narrower upward from below, a first insulating layer covering an upper portion of the first charge storage layer, and a control gate electrode on the first insulating layer and extending in the first direction, the first insulating layer having a first lowest edge and a first side edge; and   a second memory cell on the second active area, the second memory cell including a second gate insulating layer on the second active area, a second charge storage layer on the second gate insulating layer and in which a second width thereof in the first direction becomes narrower upward from below, a second insulating layer covering an upper portion of the second charge storage layer, and the control gate electrode on the second insulating layer, the second insulating layer having a second lowest edge and a second side edge, the second insulating layer being isolated the first insulating layer,   wherein a first interval between the first and second side edges in the first direction is smaller than a second interval between first and second lowest edges in the first direction.   
     
     
         3 . The nonvolatile semiconductor memory device according to  claim 2 , wherein
 the first insulating layer has a first highest edge,   the second insulating layer has a second highest edge, and   the first interval is smaller than a third interval between the first and second highest edges in the first direction.   
     
     
         4 . The nonvolatile semiconductor memory device according to  claim 2 , wherein
 the first insulating layer has a first highest edge,   the second insulating layer has a second highest edge, and   a bottom surface of the control gate electrode between the first and second active areas is above the first and second side edges and below the first and second highest edges.   
     
     
         5 . The nonvolatile semiconductor memory device according to  claim 2 , wherein
 a bottom surface of the control gate electrode between the first and second active areas is positioned around the first and second side edges.   
     
     
         6 . The nonvolatile semiconductor memory device according to  claim 2 , wherein
 an air gap is provided between lower portions of the first and second charge storage layers, and is provided below the control gate electrode.   
     
     
         7 . The nonvolatile semiconductor memory device according to  claim 2 , wherein
 the first insulating layer has a first highest edge,   the second insulating layer has a second highest edge, and   a bottom surface of the control gate electrode between the first and second active areas is above top edges of the first and second charge storage layers and below the first and second highest edges.   
     
     
         8 . The nonvolatile semiconductor memory device according to  claim 2 , wherein
 an opening is provided between the first and second side edges.   
     
     
         9 . The nonvolatile semiconductor memory device according to  claim 2 , wherein
 each of first and second charge storage layers has a cross-sectional shape in the first direction having a triangle shape or a trapezoid shape.   
     
     
         10 . The nonvolatile semiconductor memory device according to  claim 2 , wherein
 each of the first and second charge storage layers includes a floating gate electrode and a charge trap layer on the floating gate electrode.   
     
     
         11 . The nonvolatile semiconductor memory device according to  claim 10 , wherein
 each of the first and second charge storage layers includes an intermediate insulating layer between the floating gate electrode and the charge trap layer.   
     
     
         12 . A nonvolatile semiconductor memory device comprising:
 a semiconductor substrate;   first and second active areas adjacent to each other in a first direction on the semiconductor substrate;   a first memory cell on the first active area, the first memory cell including a first gate insulating layer on the first active area, a first charge storage layer on the first gate insulating layer and in which a first width thereof in the first direction becomes narrower upward from below, a first insulating layer covering an upper portion of the first charge storage layer, and a control gate electrode on the first insulating layer and extending in the first direction; and   a second memory cell on the second active area, the second memory cell including a second gate insulating layer on the second active area, a second charge storage layer on the second gate insulating layer and in which a second width thereof in the first direction becomes narrower upward from below, a second insulating layer covering an upper portion of the second charge storage layer, and the control gate electrode on the second insulating layer,   wherein a region between the upper portions of the first and second charge storage layers is filled with the first and second insulating layers.   
     
     
         13 . The nonvolatile semiconductor memory device according to  claim 12 , wherein
 the first insulating film has a first side surface,   the second insulating film has a second side surface, and   the first and second side surfaces are in contact with each other in a plane above bottom surfaces of the first and second charge storage layers.   
     
     
         14 . The nonvolatile semiconductor memory device according to  claim 12 , wherein
 the first and second insulating layers are separate layers.   
     
     
         15 . The nonvolatile semiconductor memory device according to  claim 12 , wherein
 an air gap is provided between lower portions of the first and second charge storage layers, and   the air gap is isolated from the control gate electrode by the first and second insulating layers.   
     
     
         16 . The nonvolatile semiconductor memory device according to  claim 12 , wherein
 bottom surfaces of the first and second insulating films are positioned above bottom surfaces of the first and second charge storage layers.   
     
     
         17 . The nonvolatile semiconductor memory device according to  claim 12 , wherein
 a bottom surface of the control gate electrode between the first and second active areas is above a contact portion of the first and second insulating layers.   
     
     
         18 . The nonvolatile semiconductor memory device according to  claim 12 , wherein
 a bottom surface of the control gate electrode between the first and second active areas is above top edges of the first and second charge storage layers and below top edges of the first and second insulating layers.   
     
     
         19 . The nonvolatile semiconductor memory device according to  claim 12 , wherein
 each of first and second charge storage layers has a cross-sectional shape in the first direction having a triangle shape or a trapezoid shape.   
     
     
         20 . The nonvolatile semiconductor memory device according to  claim 12 , wherein
 each of the first and second charge storage layers includes a floating gate electrode and a charge trap layer on the floating gate electrode.   
     
     
         21 . The nonvolatile semiconductor memory device according to  claim 12 , wherein
 each of the first and second charge storage layers includes an intermediate insulating layer between the floating gate electrode and the charge trap layer.