Error detection method and a system including one or more memory device

Abstract

In accordance with various embodiments, a memory device and method of error detection and correction are disclosed. A memory device may include an input for receiving a command packet including an error detection code to facilitate command error detection. The memory device may include an error manager configured to detect, based on the error detection code, whether an error occurred in transmission of the command packet, a command register configured to store the command packet and configured to provide the command packet to the error manager, and an output to transmit the command packet to a subsequent device of the point-to-point ring topology.

What is claimed is: 
     
         1 . A memory device configured for use in a point-to-point ring topology, the memory device comprising:
 an input for receiving a command packet including an error detection code to facilitate command error detection;   an error manager configured to detect, based on the error detection code, whether an error occurred in transmission of the command packet; and   a command register configured to store the command packet and configured to provide the command packet to the error manager; and   an output to transmit the command packet to a subsequent device of the point-to-point ring topology.   
     
     
         2 . The memory device of  claim 1 , wherein the error manager is further configured to determine whether the memory device can correct the error. 
     
     
         3 . The memory device of  claim 2 , wherein the error manager is further configured to correct the error if the error can be corrected. 
     
     
         4 . The memory device of  claim 1 , wherein the error manager is further configured to identify whether the error is one that may cause a memory operation that cannot be corrected. 
     
     
         5 . The memory device of  claim 4 , wherein the memory device is a flash memory device, and the memory operation consists of a selected one of a program operation and an erase operation. 
     
     
         6 . The memory device of  claim 4 , wherein the error manager is further configured to provide indication that the error is one that may cause the memory operation that cannot be corrected, in response to positive identification of such error. 
     
     
         7 . The memory device of  claim 1 , wherein the error manager can be selectively disabled. 
     
     
         8 . The memory device of  claim 7 , further comprising a control register configured to store a number of bits of information, and at least one bit indicating whether the error manager is disabled. 
     
     
         9 . The memory device of  claim 1 , wherein the memory device is a non-volatile memory device. 
     
     
         10 . The memory device of  claim 9 , wherein the non-volatile memory device is a NAND flash memory device. 
     
     
         11 . The memory device of  claim 1 , wherein the error detection code facilitates command error detection in accordance with a selected one of a Hamming code, a Cyclic Redundancy Code, a Bose-Chaudhuri-Hocquenghem code, and a Reed-Solomon code error detection scheme. 
     
     
         12 . The memory device of  claim 1 , further comprising a status register including a command packet error flag which is transmitted to the output after receiving a read status command packet on the input. 
     
     
         13 . The memory device of  claim 12 , wherein the read status command packet is a broadcast read status command packet and status register contents of the memory device are appended to status register contents of a previous device of the point-to-point ring topology received on the input. 
     
     
         14 . A method carried out within a memory device used in a point-to-point ring topology, the method comprising:
 receiving, at an input of the memory device, a command packet including an error detection code to facilitate command error detection;   detecting, at an error manager of the memory device, based on the error detection code, whether an error occurred in transmission of the command packet;   storing, at a command register of the memory device, the command packet and providing the command packet to the error manager; and   transmitting, at an output of the memory device, the command packet to a subsequent device of the point-to-point ring topology.   
     
     
         15 . The method of  claim 14 , further comprising determining whether the memory device can correct the error. 
     
     
         16 . The method of  claim 15 , further comprising correcting the error if the error can be corrected. 
     
     
         17 . The method of  claim 14 , further comprising identifying whether the error is one that may cause a memory operation that cannot be corrected. 
     
     
         18 . The method of  claim 17 , wherein the memory operation consists of a selected one of a program operation and an erase operation. 
     
     
         19 . The method of  claim 17 , further comprising generating device internal indication that the error is one that may cause the memory operation that cannot be corrected, in response to positive identification of such error. 
     
     
         20 . The method of  claim 14 , wherein the error detection code facilitates command error detection in accordance with a selected one of a Hamming code, a Cyclic Redundancy Code, a Bose-Chaudhuri-Hocquenghem code, and a Reed-Solomon code error detection scheme. 
     
     
         21 . The method of  claim 14 , further comprising:
 transmitting, by a status register of the memory device, a command packet error flag to the output after receiving a read status command packet on the input, wherein the read status command packet is a broadcast read status command packet; and   appending status register contents of the memory device to status register contents of a previous device of the point-to-point ring topology received on the input.