Mapping of random defects in a memory device

Abstract

A memory device includes a memory array with random defective memory cells. The memory array is organized into rows and columns with a row and column identifying a memory location of a memory cell of the memory array. The memory device includes a row address device and a column address device and is operative to use a grouping of either the row or the column addresses to manage the random defective memory cells by mapping the memory location of a defective memory cell to an alternate memory location.

What is claimed is: 
     
         1 . A memory device comprising:
 an apparatus coupled to a memory array, the memory array made of memory cells and organized into rows and columns of memory cells, the apparatus including,
 a row address device responsive to an incoming row address and an incoming column address, the incoming row and column addresses identifying the location of a memory cell in the memory array, the row address device operable to detect a first defective memory cell the location of which in the memory array is identified by the incoming row and column addresses, wherein upon a column of the memory array identified by the incoming column address being associated with one defective memory cell, the row address device operable to identify the location of the memory cell by an alternate row and column addresses, 
   wherein upon the column, identified by the incoming column address being associated with more than one defective memory cell, the row address device operable to identify a spare memory location identified by an alternate row and column address within the memory array and upon the column being associated with more than one defective memory cells, the row address device operable to identify two alternate row addresses identified by more than one alternate row address and one or more alternate column address.   
     
     
         2 . The memory device of  claim 1 , wherein the incoming row address identifies a row in the memory array, among a group of rows, groups of rows are each formed such that up to one defective memory cell of a given column corresponding to a group of rows is tolerated before using more than one alternate row to identify locations used to replace the location of the defective memory cells. 
     
     
         3 . The memory device of  claim 1 , wherein a column address device responsive to an incoming column address and operable to detect the incoming column address to identify a defective cell identified, in part, by the incoming column address and to replace the incoming defective column address with an alternate column address, wherein the alternate row address or alternate column address or the combination thereof to be used to identify an alternate memory cell used to store incoming data associated with an alternate memory cell identified by the alternate row address or the alternate column address or any combination thereof. 
     
     
         4 . The method of managing, as recited in  claim 1 , wherein determining that the memory cell is not defective using a predetermined value. 
     
     
         5 . The method of managing, as recited in  claim 1 , wherein determining that the memory cell is not defective using a flag. 
     
     
         6 . The method of managing, as recited in  claim 1 , wherein if it is determined that there is no match between the incoming column address and the defective column address, using the incoming column address for identifying the memory location to be accessed. 
     
     
         7 . The method of managing, as recited in  claim 1 , wherein if it is determined that there is no match between the incoming row address and the defective row address, using the incoming row address for identifying the memory location to be accessed. 
     
     
         8 . The method of managing, as recited in  claim 1 , wherein the plurality of memory cells of the memory device are random access memory (RAM) cells. 
     
     
         9 . The method of managing, as recited in  claim 1 , wherein the plurality of memory cells of the memory device are magnetic random access memory (MRAM) cells. 
     
     
         10 . The method of managing, as recited in  claim 1 , wherein using a content addressable memory (CAM) for the step of determining whether or not the incoming column address is associated with a defective memory cell.