Semiconductor memory device having data compression test circuit

Abstract

A semiconductor memory device includes a data transmission unit configured to transmit first input data to only a first global line driver or to the first global line driver and a second global line driver in response to a test signal, and a transmission element configured to transmit second input data only to the second global line driver in response to the test signal.

What is claimed is: 
     
         1 . A semiconductor memory device comprising:
 a compression unit configured to receive first and second output data and generate a compression output signal;   a first output driver configured to buffer the compression output signal and output a buffered compression signal; and   a second output driver configured to buffer the second output data and output a buffered second data.   
     
     
         2 . The semiconductor memory device of  claim 1 , wherein, when a test signal is asserted, the compression output signal indicates whether the first and second output data are the same, and when the test signal is deasserted, the compression output signal is the same as the first output data. 
     
     
         3 . The semiconductor memory device of  claim 1 , wherein the compression unit comprises:
 a determination section configured to generate a comparison signal based on whether the first and second output data are identical; and   a select output section configured to output the comparison signal as the compression output signal in response to a test signal.   
     
     
         4 . The semiconductor memory device of  claim 3 , wherein the determination section comprises an exclusive NOR gate. 
     
     
         5 . A method for testing a semiconductor memory device comprising:
 transmitting first input data to only a first global line driver or to the first global line driver and a second global line driver in response to a test signal; and   transmitting second input data only to the second global line driver in response to the test signal.   
     
     
         6 . The method of  claim 5 , wherein the first input data is transmitted to the first and the second global line drivers when the test signal is asserted, and the first input data is only transmitted to the first global line driver when the test signal is deasserted. 
     
     
         7 . The method of  claim 5 , wherein:
 the second input data is transmitted to the second global line driver when the test signal is deasserted and not transmitted to the second global line driver when the first input data when the test signal is asserted.   
     
     
         8 . The method of  claim 5 , further comprising buffering first received data to generate the first input data. 
     
     
         9 . The method of  claim 5 , further comprising buffering second received data to generate the second input data.