Microelectronic Assembly With Thermally and Electrically Conductive Underfill

Abstract

A microelectronic assembly may include a microelectronic element having a surface and a plurality of contacts at the surface; a first element consisting essentially of at least one of semiconductor or dielectric material, the first element having a surface facing the surface of the microelectronic element and a plurality of first element contacts at the surface of the first element; electrically conductive masses each joining a contact of the plurality of contacts of the microelectronic element with a respective first element contact of the plurality of first element contacts; a thermally and electrically conductive material layer between the surface of the microelectronic element and the surface of the first element and adjacent conductive masses of the conductive masses; and an electrically insulating coating electrically insulating the conductive masses and the surfaces of the microelectronic element and the first element from the thermally and electrically conductive material layer

1 . A microelectronic assembly comprising:
 a microelectronic element having a surface and a plurality of contacts at the surface;   a first element consisting essentially of at least one of semiconductor or dielectric material, the first element having a surface facing the surface of the microelectronic element and a plurality of first element contacts at the surface of the first element;   electrically conductive masses each joining a contact of the plurality of contacts of the microelectronic element with a respective first element contact of the plurality of first element contacts;   a thermally and electrically conductive material layer between the surface of the microelectronic element and the surface of the first element and adjacent conductive masses of the conductive masses; and   an electrically insulating coating electrically insulating the conductive masses and the surfaces of the microelectronic element and the first element from the thermally and electrically conductive material layer.   
     
     
         2 . The assembly of  claim 1 ,
 wherein the contacts are arranged at locations of an area array, and   wherein the conductive material layer overlies a portion of the surface of the microelectronic element coextensive with the area array.   
     
     
         3 . The assembly of  claim 1 ,
 wherein the microelectronic assembly is a microelectronic package, the first element is a substrate having terminals configured for electrically connecting the microelectronic package with a component external to the microelectronic package, and the first element contacts are electrically connected with the terminals.   
     
     
         4 . The assembly of  claim 3 ,
 wherein the surface of the substrate is a first surface, and the terminals are at a second surface of the substrate opposite from the first surface.   
     
     
         5 . The assembly of  claim 4 ,
 wherein the microelectronic element is a packaged semiconductor chip.   
     
     
         6 . The assembly of  claim 4 ,
 wherein the substrate includes a conductive element electrically connected with at least one of the terminals, and the conductive material layer is electrically connected with the conductive element.   
     
     
         7 . The assembly of  claim 1 ,
 wherein the microelectronic element is an unpackaged semiconductor chip.   
     
     
         8 . The assembly of  claim 1 ,
 wherein the insulating coating is a conformal coating that includes poly-p-xylylene.   
     
     
         9 . The assembly of  claim 1 ,
 wherein the insulating coating has a maximum thickness of about two microns.   
     
     
         10 . The assembly of  claim 1 ,
 wherein the microelectronic element is a first unpackaged semiconductor chip, and the first element is a second unpackaged semiconductor chip.   
     
     
         11 . The assembly of  claim 10 ,
 wherein the first unpackaged semiconductor chip has a second surface opposite the surface at which the contacts are disposed, and second contacts at the second surface electrically connected with the contacts, the assembly further comprising:   a third unpackaged semiconductor chip having contacts at a surface thereof facing the second contacts of the first unpackaged semiconductor chip and joined thereto by respective second electrically conductive masses;   a second thermally and electrically conductive material layer between the surface of the third unpackaged semiconductor chip and the second surface of the first unpackaged semiconductor chip and adjacent second conductive masses of the second conductive masses; and   a second electrically insulating coating electrically insulating the second conductive masses, the surface of the third unpackaged semiconductor chip and the second surface of first unpackaged semiconductor chip from the second thermally and electrically conductive material layer.   
     
     
         12 . The assembly of  claim 1 , wherein a dielectric material layer encapsulates the electrically insulating coating. 
     
     
         13 . The assembly of  claim 12 , wherein the dielectric material layer encapsulates the thermally and electrically conductive material layer. 
     
     
         14 . A method for fabricating a microelectronic assembly comprising:
 providing a microelectronic element having a surface and a plurality of contacts exposed at the surface, the contacts respectively joined by electrically conductive masses with first element contacts at a surface of a first element facing the surface of the microelectronic element, the first element consisting essentially of at least one of semiconductor or dielectric material;   providing an electrically insulating coating to the electrically conductive masses and the surfaces; and   providing a thermally and electrically conductive material layer between the surface of the microelectronic element and the surface of the first element and adjacent conductive masses of the conductive masses.   
     
     
         15 . The method of  claim 14 ,
 wherein the insulating coating is a conformal coating that has a maximum thickness of about two microns.   
     
     
         16 . The method of  claim 14 ,
 wherein the electrically insulating coating includes poly-p-xylylene.   
     
     
         17 . The method of  claim 16 ,
 wherein the providing the insulating coating includes flowing a gas including a precursor of the poly-p-xylylene at a temperature of less than 200° C.   
     
     
         18 . The method of  claim 17 ,
 wherein the providing the insulating coating includes flowing silane into a chamber containing the microelectronic element joined by the electrically conductive masses with the first element, prior to flowing the gas including the precursor of the poly-p-xylylene.   
     
     
         19 . The method of  claim 14 ,
 wherein the first element is a substrate having a plurality of terminals electrically connected with the contacts.   
     
     
         20 . The method of  claim 19 ,
 wherein the providing the thermally and electrically conductive material layer includes contacting a conductive element of the substrate with the thermally and electrically conductive material layer, the conductive element being electrically connected with a first terminal of the plurality of terminals of the substrate.   
     
     
         21 . The method of  claim 20 ,
 wherein the terminal is configured to be electrically connected with a predetermined potential.   
     
     
         22 . The method of  claim 21 ,
 wherein the predetermined potential is ground.   
     
     
         23 . The method of  claim 14 ,
 wherein the microelectronic assembly is a microelectronic package, the first element is a substrate having terminals, the terminals of the substrate include terminals configured for electrically connecting the microelectronic package with a component external to the microelectronic package and a first terminal electrically connected to the thermally and electrically conductive material layer, wherein the first terminal is configured for connection to a predetermined potential.   
     
     
         24 . The method of  claim 14  further comprising:
 providing a dielectric material layer that encapsulates the electrically insulating coating. 
 
     
     
         25 . The method of  claim 24 , wherein the dielectric material layer encapsulates the thermally and electrically conductive material layer. 
     
     
         26 . A method for fabricating a microelectronic assembly comprising:
 providing a first unpackaged semiconductor chip having a first surface opposite a second surface and a plurality of first contacts at the first and second surfaces, the contacts at the first surface respectively joined by first electrically conductive masses with contacts at a surface of a second unpackaged semiconductor chip facing the first surface, the contacts at the second surface of the first unpackaged semiconductor chip respectively joined by second electrically conductive masses with contacts at a surface of a third unpackaged semiconductor chip facing the second surface of the first unpackaged semiconductor chip;   providing an electrically insulating coating to:   the first electrically conductive masses, the first surface of the first unpackaged semiconductor chip, and the surface of the second unpackaged semiconductor chip to define a first region between the first surface of the first unpackaged semiconductor chip and the surface of the second unpackaged semiconductor chip and adjacent first electrically conductive masses of the first electrically conductive masses, and   the second electrically conductive masses, the second surface of the first unpackaged semiconductor chip and the surface of the third unpackaged semiconductor chip to define a second region between the second surface of the first unpackaged semiconductor and the surface of the third unpackaged semiconductor chip, and adjacent second electrically conductive masses of the second electrically conductive masses; and   providing the first and second regions with respective first and second thermally and electrically conductive layers.   
     
     
         27 . The method of  claim 26 ,
 wherein at least one of the second unpackaged semiconductor chip or the third unpackaged semiconductor chip includes contacts at a surface opposite from the surface facing the first chip and electrically connected to some of the first contacts.   
     
     
         28 . The method of  claim 26 , wherein the providing the electrically insulating coating comprises providing a conformal coating of poly-p-xylylene. 
     
     
         29 . The method of  claim 26 , wherein the surface of the third unpackaged semiconductor chip extends between opposing edges of the third chip and the second surface of the first unpackaged semiconductor chip extends between opposing edges of the first chip, the method further comprising:
 providing the second thermally and electrically conductive layer to extend in a direction away from the second region from at least one of the opposing edges of one chip of the first chip and the third chip towards one of the opposing edges of the other chip of the first chip and the third chip.