Redeposition Control in MRAM Fabrication Process

Abstract

Methods and structures are described to reduce metallic redeposition material in the memory cells, such as MTJ cells, during pillar etching. One embodiment forms metal studs on top of the landing pads in a dielectric layer that otherwise covers the exposed metal surfaces on the wafer. Another embodiment patterns the MTJ and bottom electrode separately. The bottom electrode mask then covers metal under the bottom electrode. Another embodiment divides the pillar etching process into two phases. The first phase etches down to the lower magnetic layer, then the sidewalls of the barrier layer are covered with a dielectric material which is then vertically etched. The second phase of the etching then patterns the remaining layers. Another embodiment uses a hard mask above the top electrode to etch the MTJ pillar until near the end point of the bottom electrode, deposits a dielectric, then vertically etches the remaining bottom electrode.

1 . An array of memory cells on a chip comprising:
 a set of landing pads electrically connected to control circuitry for the array of memory cells;   a set of metal studs disposed over the set of landing pads, with each metal stud disposed in electrical contact with one landing pad, each metal stud being embedded in a layer of dielectric material; and   a set of multi-layered memory cell pillars each having a bottom electrode and being disposed over the set of metal studs with each metal stud electrically connecting a bottom electrode in a memory cell pillar to a landing pad.   
     
     
         2 . The array of  claim 1  wherein an area of a horizontal cross section of each metal stud is less than an area of the horizontal cross section of the landing pad. 
     
     
         3 . The array of  claim 1  wherein at least some of the metal studs include a top and bottom layer of metal with the top layer of metal being co-planar with an upper surface of the dielectric material in which the metal stud is embedded. 
     
     
         4 . The array of  claim 1  wherein the memory cell pillars are oval-shaped in a top plan view and have a long axis orientation parallel to a direction of a bit line, each memory cell pillar having a metal-filled oval-shaped via formed above a top electrode in the memory cell pillar providing an electrical connection between the top electrode and the bit line. 
     
     
         5 . The array of  claim 1  wherein the memory cell pillars are circular shaped in a top plan view. 
     
     
         6 . An array of memory cells on a chip comprising:
 a set of metal studs electrically connected to control circuitry for the array of memory cells;   a set of touch-up metal layers formed on the set of metal studs with an upper surface of each touch-up metal layer being substantially co-planar with an upper surface of a dielectric material in which the each touch-up metal layer is embedded; and   a set of multi-layered memory cell pillars each having a bottom electrode and being disposed over the set of the touch-up metal layers with each touch-up metal layer electrically connecting a bottom electrode in a memory cell pillar to a metal stud.   
     
     
         7 . The array of  claim 6  wherein the memory cell pillars are oval-shaped in a top plan view and have a long axis orientation parallel to a direction of a bit line, each memory cell pillar having a metal-filled oval-shaped via formed above a top electrode in the memory cell pillar providing an electrical connection between the top electrode and the bit line. 
     
     
         8 . The array of  claim 6  wherein the memory cell pillars are circular shaped in a top plan view.