Partial block erase architecture for flash memory

Abstract

A method and system for increasing the lifespan of a flash memory device by selectively erasing sub-blocks of a memory block. Each physical memory block of the flash memory device is dividable into at least two logical sub-blocks, where each of the at least two logical sub-blocks is erasable. Therefore, only the data of the logical sub-block is erased and reprogrammed while unmodified data in the other logical sub-block avoids unnecessary program/erase cycles. The logical sub-blocks to be erased are dynamically configurable in size and location within the block. A wear leveling algorithm is used for distributing data throughout the physical and logical sub-blocks of the memory array to maximize the lifespan of the physical blocks during programming and data modification operations.

What is claimed is: 
     
         1 . (canceled) 
     
     
         2 . A method for erasing a sub-block of a memory block, the memory block having a NANO memory cell string coupled to a first wordline, a last wordline, and intermediate wordlines between the first wordline and the last wordline, comprising
 issuing a first input address command with a first address;   issuing a second input address command with a second address;   issuing a partial erase command; and,   erasing the sub-block having a set of wordlines bound by word lines corresponding to the first address and the second address.   
     
     
         3 . The method of  claim 2 , wherein the first address includes a null address. 
     
     
         4 . The method of  claim 3 , wherein the sub-block includes the set of word lines bound by one wordline corresponding to the second address and the first wordline. 
     
     
         5 . The method of  claim 2 , wherein the second address includes a null address. 
     
     
         6 . The method of  claim 5 , wherein the sub-block includes the set of wordlines bound by one wordline corresponding to the first address and the last wordline. 
     
     
         7 . The method of  claim 2 , further including erase verifying the erased sub-block. 
     
     
         8 . The method of  claim 7 , wherein erase verifying includes
 precharging a bitline coupled to the NANO memory cell string to a precharge voltage level,   biasing the set of word lines to a first voltage for turning on erased memory cells coupled to the set of word lines,   biasing unselected wordlines to a second voltage for turning on memory cells coupled to the unselected wordlines, and   sensing a change in the precharge voltage level.   
     
     
         9 . The method of  claim 8 , wherein the first voltage is a negative voltage and the second voltage is a read voltage used during a read operation. 
     
     
         10 . The method of  claim 8 , wherein the first voltage is 0V and the second voltage is a read voltage used during a read operation. 
     
     
         11 . The method of  claim 10 , wherein a common source line coupled to the NANO memory cell string is biased to a variable source bias voltage. 
     
     
         12 . The method of  claim 11 , wherein the variable source bias voltage increases from 0V to a maximum voltage as a number of the set of word lines decreases.