US2015009222A1PendingUtilityA1
Method and system for cloud based virtualized graphics processing for remote displays
Est. expiryNov 28, 2032(~6.3 yrs left)· nominal 20-yr term from priority
G06F 3/14A63F 13/355G06F 9/45504G09G 2370/022A63F 13/60A63F 13/2145A63F 13/792A63F 2300/301A63F 2300/552A63F 13/335G09G 2360/12A63F 2300/1043A63F 13/92A63F 13/48G09G 5/393A63F 13/327A63F 13/34G06T 1/20A63F 13/26A63F 13/50G06F 2009/45579G06T 2200/28A63F 2300/204G07F 17/32G06F 9/45533H04L 47/70
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Claims
Abstract
An apparatus for providing graphics processing. The apparatus includes a dual CPU socket architecture comprising a first CPU socket and a second CPU socket. The apparatus includes a plurality of GPU boards providing a plurality of GPU processors coupled to the first CPU socket and the second CPU socket, wherein each GPU board comprises two or more of the plurality of GPU processors. The apparatus includes a communication interface coupling the first CPU socket to a first subset of one or more GPU boards and the second CPU socket to a second subset of one or more GPU boards.
Claims
exact text as granted — not AI-modifiedWhat is claimed:
1 . An apparatus for providing graphics processing, comprising:
a dual CPU socket architecture comprising a first CPU socket and a second CPU socket; a plurality of GPU boards providing a plurality of GPU processors coupled to said first CPU socket and said second CPU socket, wherein each GPU board comprises two or more of said plurality of GPU processors; and a communication bus interface coupling said first CPU socket to a first subset of one or more GPU boards and said second CPU socket to a second subset of one or more GPU boards.
2 . The apparatus of claim 1 , further comprising:
a multi-core processor coupled to said first CPU socket.
3 . The apparatus of claim 2 , wherein said multi-core processor comprises a XEON E 2670 processor coupled to said first CPU socket.
4 . The apparatus of claim 1 , wherein said communication bus interface comprises:
a plurality of communication bridges each coupling a corresponding GPU board to said first CPU socket and said second CPU socket.
5 . The apparatus of claim 4 , wherein at least one of said communication bridges comprises a PCIe bridge.
5 . The apparatus of claim 5 , wherein each of said plurality of GPU boards comprises:
a bridge splitter coupled to a corresponding PCIe bridge; and two or more of said plurality of GPU processors.
6 . The apparatus of claim 5 , wherein said plurality of GPU boards are distributed across said dual CPU socket architecture symmetrically.
7 . The apparatus of claim 6 , further comprising:
a first GPU board and a second GPU board each coupled to said first CPU socket; and a third GPU board and a fourth GPU board each coupled to said second CPU socket; wherein each of said first, second, third, and fourth GPU boards comprises a two GPU processor configuration.
8 . The apparatus of claim 5 , wherein said plurality of GPU boards are distributed across said dual CPU socket architecture asymmetrically.
9 . The apparatus of claim 1 , further comprising:
a front side bus network coupling said first CPU socket and said second CPU socket;
10 . The apparatus of claim 1 , wherein said front side bus network comprises:
a QPI link communicatively coupling said first CPU socket and said second CPU socket; and a single operating system managing CPU processors coupled to said first CPU socket and said second CPU socket as supported by said QPI link.
11 . The apparatus of claim 1 , wherein at least one of said plurality of graphics processors comprises an Nvidia GK107 graphics processor chip.
12 . The apparatus of claim 1 , wherein a GPU processor supports a virtual machine in a one-to-one relationship.
13 . The apparatus of claim 1 , further comprising:
a plurality of virtualized GPU processors supported by said plurality of GPU processors, wherein a virtualized GPU supports a virtual machine.
14 . The apparatus of claim 1 , wherein said dual CPU socket architecture is configured in a Sandy bridge configuration.
15 . The apparatus of claim 1 , wherein said plurality of GPU boards are identical.
16 . The apparatus of claim 1 , wherein said dual CPU socket architecture and said plurality of GPU boards support a plurality of virtual machines each comprising portions of one or more CPU cores and one or more GPU processors.
17 . The apparatus of claim 1 , wherein said dual CPU socket architecture and said plurality of GPU boards are implemented within a pseudo virtual machine system operating under a single operating system and running multiple applications for one or more end users.
18 . A network attached GPU device, comprising:
a plurality of processing boards providing a plurality of virtual CPU and GPU processors, wherein each of said processing boards comprises:
a dual CPU socket architecture comprising a first CPU socket and a second CPU socket;
a plurality of GPU boards providing a plurality of GPU processors coupled to said first CPU socket and said second CPU socket, wherein each GPU board comprises two or more of said plurality of GPU processors;
a first plurality of communication bridges each coupling a corresponding GPU board to said first CPU socket and said second CPU socket; and
a communication interface coupling said first CPU socket to a first subset of one or more GPU boards and said second CPU socket to a second subset of one or more GPU boards.
19 . The apparatus of claim 18 , wherein each of said plurality of GPU boards comprises:
a bridge splitter coupled to a corresponding communication bridge; and two or more of said plurality of GPU processors.
20 . The apparatus of claim 18 , wherein said plurality of GPU boards are distributed across said dual CPU socket architecture symmetrically such that a first GPU board and a second GPU board each coupled to said first CPU socket and a third GPU board and a fourth GPU board each coupled to said second CPU socket, wherein each of said first, second, third, and fourth GPU boards comprises a two GPU processor configuration.
21 . The network attached GPU device of claim 18 , further comprising:
a plurality of computing device emulators supported by said plurality of processing boards.Join the waitlist — get patent alerts
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