Semiconductor device and manufacturing method of semiconductor device

Abstract

According to one embodiment, a semiconductor device includes a plurality of wires arranged in parallel at a predetermined pitch, a plurality of first contacts that are each connected to an odd-numbered wire among the wires and are arranged in parallel in an orthogonal direction with respect to a wiring direction of the wires, and a plurality of second contacts that are each connected to an even-numbered wire among the wires and are arranged in parallel in an orthogonal direction with respect to the wiring direction of the wires in such a way as to be offset from the first contacts in the wiring direction of the wires, in which the first contacts are offset from the second contacts by a pitch of the wires in an orthogonal direction with respect to the wiring direction of the wires.

1 - 7 . (canceled) 
     
     
         8 . A manufacturing method of a semiconductor device comprising:
 forming core patterns, onto which a plurality of linear shaped first mask patterns, each of which is offset in a middle by a wiring pitch in an orthogonal direction with respect to a wiring direction, is transferred, on a processing target layer;   forming first sidewall patterns on sidewalls of the core patterns;   removing the core patterns while leaving the first sidewall patterns on the processing target layer;   forming a second mask pattern that covers part of a space between the first sidewall patterns on the processing target layer; and   forming first openings in the processing target layer by processing the processing target layer exposed from the first sidewall patterns and the second mask pattern.   
     
     
         9 . The manufacturing method of a semiconductor device according to  claim 8 , wherein a width of the first mask patterns and an interval between the first mask patterns are twice the wiring pitch. 
     
     
         10 . The manufacturing method of a semiconductor device according to  claim 8 , further comprising slimming the core patterns before forming the first sidewall patterns. 
     
     
         11 . The manufacturing method of a semiconductor device according to  claim 8 , further comprising:
 forming an active area isolated by a trench in a NAND flash memory;   forming the processing target layer on the active area;   embedding a contact material in the first openings; and   forming an upper layer wire connected to the active area via the contact material on the processing target layer.   
     
     
         12 . The manufacturing method of a semiconductor device according to  claim 8 , further comprising:
 forming a lower layer wire on an underlying layer;   forming the processing target layer on the lower layer wire;   embedding a contact material in the first openings; and   forming an upper layer wire connected to the lower layer wire via the contact material on the processing target layer.   
     
     
         13 . The manufacturing method of a semiconductor device according to  claim 8 , further comprising:
 forming a mask layer before forming the core patterns on the processing target layer;   forming second openings in the mask layer by processing the mask layer exposed from the first sidewall patterns and the second mask pattern;   forming third openings surrounded by second sidewall patterns by forming the second sidewall patterns on sidewalls of the second openings; and   forming the first openings in the processing target layer by transferring the third openings onto the processing target layer.   
     
     
         14 . The manufacturing method of a semiconductor device according to  claim 8 , wherein a width of the first mask patterns and an interval between the first mask patterns are four times the wiring pitch. 
     
     
         15 . The manufacturing method of a semiconductor device according to  claim 14 , wherein the width of the first sidewall patterns and the interval between the first sidewall patterns are reduced to a half every time formation of the first sidewall patterns is repeated with the first sidewall patterns as a core pattern. 
     
     
         16 . A semiconductor device comprising:
 a plurality of wires arranged in parallel at a predetermined pitch;   a plurality of first contacts that are each connected to an odd-numbered wire among the wires and are arranged in parallel in an orthogonal direction with respect to a wiring direction of the wires; and   a plurality of second contacts that are each connected to an even-numbered wire among the wires and are arranged in parallel in an orthogonal direction with respect to the wiring direction of the wires in such a way as to be offset from the first contacts in the wiring direction of the wires, wherein   the first contacts are offset from the second contacts by a pitch of the wires in an orthogonal direction with respect to the wiring direction of the wires.   
     
     
         17 . The semiconductor device according to  claim 16 , wherein a pitch PH of the wires satisfies a relationship
   PH<0.25*λ/NA
   
       where λ is an exposure wavelength in lithography and NA is a numerical aperture in a projection optical system. 
     
     
         18 . The semiconductor device according to  claim 16 , wherein an accuracy of an interval between the first contact and the second contact is equal to an accuracy of the pitch of the wires. 
     
     
         19 . The semiconductor device according to  claim 16 , wherein the wires are bit lines of a NAND flash memory. 
     
     
         20 . The semiconductor device according to  claim 19 , wherein, in an active area isolated from each other by a trench, the bit lines are connected to a high-concentration impurity diffusion layer between select gate lines via the first contacts and the second contacts, respectively.