Partially recessed channel core transistors in replacement gate flow

Abstract

An integrated circuit containing MOS transistors with replacement gates may be formed with elevated LDD regions and/or recessed replacement gates on a portion of the transistors. Elevating the LDD regions is accomplished by a selective epitaxial process prior to LDD implant. Recessing the replacement gates is accomplished by etching substrate material after removal of sacrificial gate material and before formation of a replacement gate dielectric layer. Elevating the LDD regions and recessing the replacement gates may increase a channel length of the MOS transistors and thereby desirably increase threshold uniformity of the transistors.

What is claimed is: 
     
         1 . An integrated circuit, comprising:
 a substrate comprising semiconductor material;   a first metal oxide semiconductor (MOS) transistor, comprising a first replacement gate disposed on a first dielectric layer and a first channel, wherein the first channel extends adjacent the first dielectric layer along both a horizontal and a vertical surface; and   a second MOS transistor comprising a second replacement gate disposed on a second dielectric layer and a second channel, wherein the second channel extends adjacent the second dielectric layer along a horizontal surface and not a vertical surface;   in which:   said first dielectric layer and said second dielectric layer have substantially equal composition;   said first replacement gate and said second replacement gate have substantially equal composition; and   said first MOS transistor and said second MOS transistor have a same polarity.   
     
     
         2 . The integrated circuit of  claim 1 , in which a first gate linewidth of said recessed first replacement gate is substantially equal to a second gate linewidth of said second replacement gate. 
     
     
         3 . The integrated circuit of  claim 1 , in which a first gate linewidth of said first replacement gate is 80 to 90 percent of a second gate linewidth of said second replacement gate. 
     
     
         4 . The integrated circuit of  claim 1 , in which said first MOS transistor is part of a static random access memory (SRAM) circuit. 
     
     
         5 . The integrated circuit of  claim 1 , in which said second MOS transistor is part of a logic circuit. 
     
     
         6 . The integrated circuit of  claim 1 , in which said first replacement gate is recessed 2 to 50 nanometers below said top surface of said substrate. 
     
     
         7 . The integrated circuit of  claim 6 , in which a surface of said substrate under said first dielectric layer is substantially coplanar with a surface of field oxide under said first dielectric layer. 
     
     
         8 . The integrated circuit of  claim 6 , in which:
 said first MOS transistor further comprises elevated lightly doped drain (LDD) regions; and   said second MOS transistor further comprises LDD regions which are not elevated.   
     
     
         9 . The integrated circuit of  claim 1 , in which:
 said first MOS transistor further comprises elevated LDD regions; and   said second MOS transistor further comprises LDD regions which are not elevated.   
     
     
         10 . A method of forming an integrated circuit, comprising the steps of:
 providing a substrate comprising semiconductor material;   concurrently removing a first sacrificial gate in a first MOS transistor and removing a second sacrificial gate in a second MOS transistor;   concurrently removing a first sacrificial gate dielectric layer in said first MOS transistor and removing a second sacrificial gate dielectric layer in said second MOS transistor;   forming an etch mask over said substrate in said first MOS transistor so as to expose said substrate in said first MOS transistor;   removing semiconductor material from said substrate in an area for a recessed replacement gate in said first MOS transistor, such that an etched surface of said substrate is substantially coplanar with an etched surface of field oxide adjacent to said etched surface of said substrate, and such that semiconductor material is not removed from said substrate in said second MOS transistor;   concurrently forming a first replacement gate dielectric layer in said first MOS transistor and forming a second replacement gate dielectric layer in said second MOS transistor; and   concurrently forming a recessed first replacement gate on said first replacement gate dielectric layer and forming a second replacement gate on said second replacement gate dielectric layer;   so that said recessed first replacement gate is recessed below a top surface of said substrate and said first MOS transistor and said second MOS transistor have a same polarity.   
     
     
         11 . The method of  claim 10 , in which a first replacement gate linewidth of said recessed first replacement gate is substantially equal to a second replacement gate linewidth of said second replacement gate. 
     
     
         12 . The method of  claim 10 , in which a first replacement gate linewidth of said recessed first replacement gate is 80 to 90 percent of a second replacement gate linewidth of said second replacement gate. 
     
     
         13 . The method of  claim 10 , further comprising the steps:
 forming an epi-block layer over said second MOS transistor so as to cover said substrate adjacent to said second sacrificial gate and expose said substrate adjacent to said first sacrificial gate;   forming elevated LDD semiconductor regions adjacent to said first sacrificial gate by a selective epitaxial growth process while said epi-block layer is in place, so that elevated LDD semiconductor regions are not formed adjacent to said second sacrificial gate;   removing said epi-block layer; and   subsequently implanting dopants into said elevated LDD semiconductor regions to form first LDD implanted regions into said substrate adjacent to said second sacrificial gate to form second LDD implanted regions, before said step of concurrently removing said first sacrificial gate and said second sacrificial gate, so that said second LDD implanted regions are not elevated.   
     
     
         14 . The method of  claim 10 , in which said first MOS transistor is part of an SRAM circuit. 
     
     
         15 . The method of  claim 10 , in which said second MOS transistor is part of an logic circuit. 
     
     
         16 . A method of forming an integrated circuit, comprising the steps of:
 providing a substrate comprising semiconductor material;   forming an epi-block layer over a second MOS transistor so as to cover said substrate adjacent to a second sacrificial gate of said second MOS transistor and expose said substrate adjacent to a first sacrificial gate of a first MOS transistor;   forming elevated LDD semiconductor regions adjacent to said first sacrificial gate by a selective epitaxial growth process while said epi-block layer is in place, so that elevated LDD semiconductor regions are not formed adjacent to said second sacrificial gate;   removing said epi-block layer;   subsequently implanting dopants into said elevated LDD semiconductor regions to form first LDD implanted regions into said substrate adjacent to said second sacrificial gate to form second LDD implanted regions, so that said second LDD implanted regions are not elevated;   concurrently removing said first sacrificial gate and removing said second sacrificial gate;   concurrently removing a first sacrificial gate dielectric layer in said first MOS transistor and removing a second sacrificial gate dielectric layer in said second MOS transistor;   concurrently forming a first replacement gate dielectric layer in said first MOS transistor and forming a second replacement gate dielectric layer in said second MOS transistor; and   concurrently forming a recessed first replacement gate on said first replacement gate dielectric layer and forming a second replacement gate on said second replacement gate dielectric layer.   
     
     
         17 . The method of  claim 16 , in which a first replacement gate linewidth of said recessed first replacement gate is substantially equal to a second replacement gate linewidth of said second replacement gate. 
     
     
         18 . The method of  claim 16 , in which a first replacement gate linewidth of said recessed first replacement gate is 80 to 90 percent of a second replacement gate linewidth of said second replacement gate. 
     
     
         19 . The method of  claim 16 , in which said first MOS transistor is part of an SRAM circuit. 
     
     
         20 . The method of  claim 16 , in which said second MOS transistor is part of an logic circuit.