Processors having heterogeneous cores with different instructions and/or architecural features that are presented to software as homogeneous virtual cores

Abstract

A processor of an aspect includes a first heterogeneous physical compute element having a first set of supported instructions and architectural features, and a second heterogeneous physical compute element having a second set of supported instructions and architectural features. The second set of supported instructions and architectural features is different than the first set of supported instructions and architectural features. The processor also includes a workload and architectural state migration module coupled with the first and second heterogeneous physical compute elements. The workload and state migration module is operable to migrate a workload and associated architectural state from the first heterogeneous physical compute element to the second heterogeneous physical compute element in response to an attempt by the workload to perform at least one of an unsupported instruction and an unsupported architectural feature on the first heterogeneous physical compute element.

What is claimed is: 
     
         1 . A processor comprising:
 a first heterogeneous physical compute element having a first set of supported instructions and architectural features;   a second heterogeneous physical compute element having a second set of supported instructions and architectural features, the second set of supported instructions and architectural features being different than the first set of supported instructions and architectural features; and   a workload and architectural state migration module coupled with the first and second heterogeneous physical compute elements, the workload and state migration module to migrate a workload and associated architectural state from the first heterogeneous physical compute element to the second heterogeneous physical compute element in response to an attempt by the workload to perform at least one of an unsupported instruction and an unsupported architectural feature on the first heterogeneous physical compute element.   
     
     
         2 . The processor of  claim 1 , wherein the workload and architectural state migration module is to migrate the workload and the associated architectural state to the second heterogeneous physical compute element in response to the attempt to perform the unsupported instruction that is not included in the first set of supported instructions and architectural features. 
     
     
         3 . The processor of  claim 2 , wherein the workload and architectural state migration module is be notified of the attempt to perform the unsupported instruction without a corresponding exceptional condition being provided to software. 
     
     
         4 . The processor of  claim 1 , wherein the workload and architectural state migration module is to migrate the workload and the associated architectural state to the second heterogeneous physical compute element in response to the attempt to perform the unsupported architectural feature that is not included in the first set of supported instructions and architectural features. 
     
     
         5 . The processor of  claim 1 , wherein a majority of instructions of the first set of supported instructions are in the second set of supported instructions. 
     
     
         6 . The processor of  claim 1 , wherein the workload and architectural state migration module is to migrate the workload and the associated architectural state transparently to software that is to have scheduled the workload on the processor. 
     
     
         7 . The processor of  claim 1 , wherein the processor is to expose a plurality of homogeneous virtual cores to software that is to schedule workloads on the plurality of homogeneous virtual cores, and wherein the plurality of homogeneous virtual cores are to appear to the software to support identical sets of instructions and architectural features. 
     
     
         8 . The processor of  claim 1 , wherein the second set of supported instructions and architectural features is a superset of the first set of supported instructions and architectural features. 
     
     
         9 . The processor of  claim 1 , wherein the first and second heterogeneous physical compute elements comprise cores. 
     
     
         10 . The processor of  claim 1 , wherein the first heterogeneous physical compute element comprises a relatively lower overall power consumption and relatively lower overall computation capability core, wherein the second heterogeneous physical compute element comprises a relatively higher overall power consumption and relatively higher overall computation capability core. 
     
     
         11 . The processor of  claim 1 , wherein the workload and architectural state migration module is to maintain information about which instructions and which architectural features are supported by the second heterogeneous physical compute element. 
     
     
         12 . A method performed by a processor comprising:
 performing a workload on a first heterogeneous physical compute element having a first set of supported instructions and architectural features;   detecting an attempt by the workload to perform at least one of an unsupported instruction and an unsupported architectural feature, the at least one not supported by the first set of supported instructions and architectural features, on the first heterogeneous physical compute element; and   migrating the workload and associated architectural state from the first heterogeneous physical compute element to a second heterogeneous physical compute element in response to the detection of the attempt, the second heterogeneous physical compute element having a second set of supported instructions and architectural features, which include the at least one of the unsupported instruction and the unsupported architectural feature.   
     
     
         13 . The method of  claim 12 , wherein detecting comprises detecting the attempt to perform the unsupported instruction which is not included in the first set of supported instructions and architectural features, and wherein the unsupported instruction is included in the second set of supported instructions and architectural features. 
     
     
         14 . The method of  claim 13 , wherein migrating comprises migrating the workload without an exceptional condition being provided to software as a result of the attempt to perform the unsupported instruction. 
     
     
         15 . The method of  claim 12 , wherein detecting comprises detecting the attempt to perform the unsupported architectural feature which is not included in the first set of supported instructions and architectural features, and wherein the unsupported architectural feature is included in the second set of supported instructions and architectural features. 
     
     
         16 . The method of  claim 12 , wherein a majority of instructions of the first set of supported instructions and architectural features are included in the second set of supported instructions and architectural features. 
     
     
         17 . The method of  claim 12 , wherein migrating comprises migrating the workload and architectural state transparently to software that is to have scheduled the workload on the processor. 
     
     
         18 . The method of  claim 12 , further comprising exposing a plurality of homogeneous virtual cores to software that is to schedule workloads on the plurality of homogeneous virtual cores. 
     
     
         19 . The method of  claim 12 , wherein migrating comprises migrating to the second heterogeneous physical compute element having the second set of supported instructions and architectural features that is a superset of the first set of supported instructions and architectural features. 
     
     
         20 . The method of  claim 12 , wherein migrating comprises migrating from a relatively lower overall power consumption and relatively lower overall computation capability core to a relatively higher overall power consumption and relatively higher overall computation capability core. 
     
     
         21 . The method of  claim 12 , further comprising maintaining information in the processor about which instructions and which architectural features are supported by the second heterogeneous physical compute element. 
     
     
         22 . A system to process instructions comprising:
 an interconnect;   a dynamic random access memory (DRAM) coupled with the interconnect; and   a processor coupled with the interconnect, the processor comprising:   a first heterogeneous physical core having a first instruction set;   a second heterogeneous physical core having a second instruction set that is different than the first instruction set; and   a workload and architectural state migration module coupled with the first and second heterogeneous physical cores, the workload and state migration module to migrate a workload and associated architectural state from the first heterogeneous physical core to the second heterogeneous physical core in response to an attempt by the workload to perform an unsupported instruction that is not included in the first instruction set on the first heterogeneous physical core.   
     
     
         23 . The system of  claim 22 , wherein the second instruction set is a superset of the first instruction set, and wherein the first heterogeneous physical core comprises a relatively lower power consumption and relatively lower computation capability core and the second heterogeneous physical core comprises a relatively higher power consumption and relatively higher computation capability core.