System and method for responding to failure of a hardware locus at a communication installation

Abstract

A method for responding to a failure of hardware locus of at a communication installation having a plurality of control apparatuses for controlling a plurality of processes distributed among a plurality of hardware loci, the hardware loci including at least one spare hardware locus, includes the steps of: (a) Shifting control of a failed process from an initial control apparatus to an alternate control apparatus located at an alternate hardware locus than the failed hardware locus. The failed process is a respective process controlled by the initial control apparatus located at the failed hardware locus. (b) Relocating the respective control apparatuses located at the failed hardware locus to a spare hardware locus. (c) Shifting control of the failed process from the alternate control apparatus to the initial control apparatus relocated at the spare hardware locus.

What is claimed is: 
     
         1 . A system for effecting continuity of operation of a plurality of processes, the system comprising:
 a plurality of primary processors, each primary processor being configured to run a respective one of the plurality of processes and being located at a respective location of a plurality of locations; and   a plurality of secondary processors, each secondary processor being associated with at least one primary processor of the plurality of primary processors and being configured to run at least the respective one of the plurality of processes which the at least one associated primary processor is configured to run should the at least one associated primary processor fail, each secondary processor being located at a respective location of the plurality of locations such that no primary processor is located at a same location as its associated secondary processor, wherein each secondary processor is located at a respective location of the plurality of locations of at least one primary processor, the at least one primary processor not being associated with the secondary processor at the same location.