Evict on write, a management strategy for a prefetch unit and/or first level cache in a multiprocessor system with speculative execution

Abstract

In a multiprocessor system with at least two levels of cache, a speculative thread may run on a core processor in parallel with other threads. When the thread seeks to do a write to main memory, this access is to be written through the first level cache to the second level cache. After the write though, the corresponding line is deleted from the first level cache and/or prefetch unit, so that any further accesses to the same location in main memory have to be retrieved from the second level cache. The second level cache keeps track of multiple versions of data, where more than one speculative thread is running in parallel, while the first level cache does not have any of the versions during speculation. A switch allows choosing between modes of operation of a speculation blind first level cache.

1 . In a parallel processing system comprising a plurality of cores, at least first and second levels of cache, a method comprising:
 maintaining the first level cache responsive to selectively operable in accordance with at least first and second modes of speculation blind addressing; and   choosing one of the first and second modes, responsive to program related considerations.   
     
     
         2 . The method of  claim 1 , wherein the program related considerations comprise whether speculation is short running or long running. 
     
     
         3 . The method of  claim 1 , wherein the first and second modes comprise
 evicting a line from the L1 on write; and   maintaining a multi-piece address space in the L1, wherein each thread has a separate space that gives the illusion of no speculation.   
     
     
         4 . The method of  claim 1 , wherein choosing is responsive to a programmable switch. 
     
     
         5 . A processor for use in a multiprocessor system, the processor comprising
 means for communicating with a communications pathway, the pathway comprising first and second level caches;   means for switching between at least two modes of using the first and second level caches, both modes allowing the first level cache and/or prefetch unit to be operated in a speculation blind manner.   
     
     
         6 . The processor of  claim 5 , wherein the modes comprise:
 a first mode where, responsive to a write from a speculative thread, at least one line corresponding to results is evicted from the first level cache and/or prefetch unit and recorded in the second level cache; and   a second mode where, responsive to a write from a speculative thread, the first level cache stores results.   
     
     
         7 . A system comprising the processor of  claim 6 , a prefetch unit, and a first level cache, wherein,
 in the second mode, upon completion of a speculative thread, the first level cache and/or prefetch unit is cleared and any data needed by other speculative threads must be reloaded from the second level cache; and   in the first mode, the first level cache and/or prefetch unit does not need to be cleared after completion of a speculative thread.   
     
     
         8 . A system comprising the processor of  claim 6 , a prefetch unit, and a first level cache, wherein the operations comprise, responsive to selection of the first mode:
 determining whether a speculative thread seeks to write;   upon a positive determination, writing from the speculative thread through the first level cache to the second level cache;   evicting a line from the first level cache and/or prefetch unit corresponding to the writing; and   resolving speculation downstream from the first level cache.   
     
     
         9 . The system of  claim 8 , wherein the operations comprise, subsequent to evicting, if a speculative thread seeks to access an address corresponding to the evicted line, retrieving an appropriate version of data from the second level cache. 
     
     
         10 . The system of  claim 8 , wherein the operations comprise tagging data retrieved from the second level cache, when there are multiple versions. 
     
     
         11 . The system of  claim 10 , wherein the operations comprise, in the second level cache, not storing responsive to such tagging. 
     
     
         12 . The system of  claim 8 , wherein the operations comprise, when a speculative thread reads from the first level cache and/or prefetch unit, notifying the second level cache. 
     
     
         13 . The system of  claim 12 , wherein the second level cache checks its coherence data when receiving an L1 hit notification for whether the L1 could have had a stale copy, and if so, subsequently invalidates an associated speculation. 
     
     
         14 . The system of  claim 8 , wherein the operations comprise:
 determining whether a speculation has completed; and   if speculation has completed, allowing the first level cache to store results.   
     
     
         15 . A computer program product adapted to operate in a speculative multiprocessor environment, the computer program product comprising:
 a storage medium readable by a processing circuit and storing instructions run by the processing circuit for carrying out a method comprising:   maintaining a speculative thread;   responsive to whether speculation is expected to be long or short running, choosing a mode of operation of a speculation blind cache memory.   
     
     
         16 . The product of  claim 15 , wherein, for short running speculation, the mode of operation comprises
 writing through to a downstream cache; and   evicting a line from the first level cache and/or prefetch unit.   
     
     
         17 . The product of  claim 15 , wherein, for long running speculation, the mode of operation comprises address aliasing in which the cache memory and/or prefetch unit maintains a plurality of address spaces, a respective one corresponding to each speculative thread, such that within each address space it appears to the corresponding thread that it has an entire physical memory to itself without any other speculative threads conflicting for use of the physical memory.