Efficient Post Write Read in Three Dimensional Nonvolatile Memory

Abstract

Data that is stored in a higher error rate format in a 3-D nonvolatile memory is backed up in a lower error rate format. Later, the higher error rate copy is sampled to determine if it is acceptable. A sampling pattern samples all word lines of a string and at least one word line of each string of the block.

It is claimed: 
     
         1 . A method of operating a 3-D nonvolatile memory array comprising:
 writing data in a first format in a plurality of separately selectable sets of strings of a first block;   writing the data in a second format in at least a second block;   subsequently sampling the data written in the first format from the first block, sample data including: (i) data of all word lines of a sample set of strings and (ii) a sample word line of each of the sets of strings of the plurality;   if the sampled data meets a standard, then discarding the data written in the second format in the at least a second block; and   if the sampled data does not meet the standard, then discarding the data in the first format in the first block.   
     
     
         2 . The method of  claim 1  further comprising, if the sample data does not meet the standard, then using the data in the second format from the at least a second block as a source to write the data in the first format in a third block. 
     
     
         3 . The method of  claim 1  wherein the standard requires that fewer than a threshold number of bits of the sample data are different to corresponding bits of the data written in the second format from the at least a second block. 
     
     
         4 . The method of  claim 1  wherein the first format produces a higher error rate than the second format. 
     
     
         5 . The method of  claim 4  wherein the first format is a Multi Level Cell (MLC) format and the second format is a Single Level Cell (SLC) format. 
     
     
         6 . The method of  claim 4  wherein the first format is an MLC format that stores n-bits per cell, where n=2, 3, 4, or more, and the second format is an SLC format or an MLC format that stores n-bits or fewer than n-bits per cell. 
     
     
         7 . The method of  claim 5  wherein the first format includes a lower bit and an upper bit in a memory cell and the sample data includes both lower bits and upper bits. 
     
     
         8 . The method of  claim 5  wherein the first format includes a lower bit and an upper bit in a memory cell and the sample data consists of upper bits. 
     
     
         9 . The method of  claim 5  wherein the first format is a two-bit per cell MLC format and the at least a second block consists of two SLC blocks. 
     
     
         10 . The method of  claim 1  wherein the sampling is performed in response to determining that a number of erased blocks remaining in the 3-D nonvolatile memory array is less than a threshold number. 
     
     
         11 . The method of  claim 1  wherein word lines are written in a predetermined order and the sample word line is the first written word line according to the predetermined order. 
     
     
         12 . The method of  claim 1  wherein the first block shares a block select circuit with a third block, and the first and third blocks are sampled together after they are both fully written. 
     
     
         13 . The method of  claim 12  wherein the third block is sampled such that sample data includes: (i) data of all word lines of a sample set of strings of the third block and (ii) a sample word line of each set of strings of the third block. 
     
     
         14 . A 3-D nonvolatile memory array comprising:
 a plurality of individually erasable blocks, a block including a plurality of strings connected to each bit line of the block, each string along a bit line being selectable by a different select line so that an individual select line selects a set of strings of different bit lines;   a write circuit that is configured to write data in a first set of blocks in a first format and to write the data to a second set of blocks in a second format;   a sampling circuit that is configured to sample the data in the first format, from a block of the first set of blocks, sample data including (i) all word lines of a sample set of strings in the block, and (ii) a sample word line of each set of strings of the block;   a determination circuit that is configured to determine whether the sample data meets a standard; and   a block reclaim circuit that is configured to reclaim a portion of the second set of blocks containing the data in the second format if the sample data meets the standard, and configured to reclaim a portion of the first set of blocks containing the data in the first format if the sample data does not meet the standard.   
     
     
         15 . The 3-D nonvolatile memory array of  claim 14  further comprising a data copying circuit that is configured to use the data in the second format in the second set of blocks as a source to write the data in the first set of blocks in the first format. 
     
     
         16 . The 3-D nonvolatile memory array of  claim 14  wherein the determination circuit is configured to compare the sample data with corresponding portions of data from the second set of blocks to identify a number of bits that are different and to compare the number with a threshold number. 
     
     
         17 . The 3-D nonvolatile memory array of  claim 14  wherein the second format provides a lower error rate than the first format. 
     
     
         18 . The 3-D nonvolatile memory array of  claim 17  wherein the first format is a Multi Level Cell (MLC) format and the second format is a Single Level Cell (SLC) format. 
     
     
         19 . The 3-D nonvolatile memory array of  claim 17  wherein the first format is an MLC format that stores n-bits per cell, where n=2, 3, 4, or more, and the second format is an SLC format or an MLC format that stores n-bits or fewer than n-bits per cell. 
     
     
         20 . The 3-D nonvolatile memory array of  claim 19  wherein the first format includes a lower bit and an upper bit in each memory cell and the sampling circuit is configured to sample both lower bits and upper bits. 
     
     
         21 . The 3-D nonvolatile memory array of  claim 19  wherein the first format includes a lower bit and an upper bit in each memory cell and the sampling circuit is configured to sample only upper bits. 
     
     
         22 . The 3-D nonvolatile memory array of  claim 19  wherein the first format is a two-bit per cell MLC format and the at least a second block consists of two SLC blocks. 
     
     
         23 . The 3-D nonvolatile memory array of  claim 14  wherein the sampling circuit performs sampling in response to determining that a number of erased blocks remaining in the 3-D nonvolatile memory array is less than a threshold number. 
     
     
         24 . The 3-D nonvolatile memory array of  claim 14  wherein word lines are written in a predetermined order and the sample word line is the first written word line according to the predetermined order. 
     
     
         25 . The 3-D nonvolatile memory array of  claim 14  wherein the plurality of individually erasable blocks are arranged in pairs, with each pair of blocks sharing a block select circuit, and wherein the sampling circuit is configured to sample the data in the first format from a pair of blocks together. 
     
     
         26 . The 3-D nonvolatile memory array of  claim 25  wherein the sampling circuit is configured to sample a pair of blocks such that sample data includes: (i) data of all word lines of a sample set of strings in each block and (ii) a sample word line of each set of strings of each blocks. 
     
     
         27 . A method of operating a 3-D nonvolatile memory array in which pairs of blocks share block select circuits comprising:
 writing data in a first format in a plurality of separately selectable sets of strings of a first block and a second block that share block select circuits;   writing the data in a second format in at least a third block;   subsequently, after the first and second blocks are fully written, sampling the data written in the first format from the first and second blocks, sample data including: (i) data of all word lines of a first sample set of strings of the first block and data of all word lines of a second sample set of strings of the second block, and (ii) a sample word line of each of the sets of strings of the first block and a sample word line of each of the sets of strings of the second block;   if the sampled data meets a standard, then discarding the data written in the second format in the at least a third block; and   if the sampled data does not meet the standard, then discarding the data in the first format in the first and second blocks.   
     
     
         28 . The method of  claim 27  wherein writing the data in the first format consists of writing at least two two-bit per cell MLC format blocks and writing the data in the second format consists of writing at least four SLC blocks. 
     
     
         29 . A method of operating a 3-D nonvolatile memory array in which word lines of a block are formed as groups of commonly connected word lines, comprising:
 writing data in a first format in a plurality of separately selectable sets of strings of a first block;   writing the data in a second format in at least a second block;   subsequently sampling the data written in the first format from the first block, sample data including: (i) data of at least one sample word line from each group of commonly connected word lines, and (ii) data of at least a sample word line of each of the sets of strings of the plurality;   if the sampled data meets a standard, then discarding the data written in the second format in the at least a second block; and   if the sampled data does not meet the standard, then discarding the data in the first format in the first block.   
     
     
         30 . The method of  claim 29  wherein sample word lines are chosen according to a pattern that is derived from data obtained from memory operation. 
     
     
         31 . The method of  claim 30  wherein the pattern is obtained from Error Correction Code (ECC) data, or wear pattern data. 
     
     
         32 . The method of  claim 29  wherein sample word lines are chosen according to a physical location of the first block in the 3-D nonvolatile memory array.