Methods of Forming Conductive Materials on Contact Pads

Abstract

Methods of forming conductive materials on contact pads for semiconductor devices and packages. Substrate is provided with contact pads formed thereon. Conductive material is formed over the contact pads by a depositing process followed by a heating process to alter the chemical properties of the conductive material. Optionally, a dispersing process may be incorporated. An interconnect structure can be mounted over the conductive material where the interconnect structure is attached to the conductive material without any active treatment to the conductive material after formation.

What is claimed is: 
     
         1 . A method comprising:
 (a) providing a substrate having an upper surface and a lower surface, the lower surface opposite the upper surface;   (b) forming a contact pad over the upper surface of the substrate;   (c) forming a conductive material over the contact pad including:
 (i) depositing the conductive material; 
 (ii) dispersing the conductive material from an initial area to a final area, the final area greater than the initial area; 
 (iii) heating the conductive material; and 
   (d) mounting an interconnect structure over the conductive material, wherein the interconnect structure is attached to the conductive material without any active treatment to the conductive material after the forming step (c).   
     
     
         2 . The method of  claim 1 , further comprising:
 (e) mounting a semiconductor package over the interconnect structure, the semiconductor package having an integrated circuit device.   
     
     
         3 . The method of  claim 2 , further comprising:
 (f) forming a plurality of external interconnects on the lower surface of the substrate, the external interconnects in communication with the integrated circuit device.   
     
     
         4 . The method of  claim 1 , wherein the depositing step (i) of the forming step (c) includes depositing the conductive material including at least one of silver (Ag), platinum (Pt), gold (Au), copper (Cu), carbon nanotube (CNT), graphene, organic metal, and mixtures thereof. 
     
     
         5 . The method of  claim 1 , wherein the forming step (c) includes forming the conductive material over the contact pad to prevent oxidation of the contact pad. 
     
     
         6 . The method of  claim 1 , further comprising:
 treating the contact pads with hydrophilic plasma prior to the forming step (c).   
     
     
         7 . A method comprising:
 (a) providing a substrate having an upper surface and a lower surface, the lower surface opposite the upper surface;   (b) forming first and second sets of contact pads over the upper surface of the substrate, the first set of contact pads disposed about a central region of the substrate and the second set of contact pads disposed about a peripheral region of the substrate;   (c) mounting an integrated circuit device over the first set of contact pads;   (d) forming a conductive material over the second set of contact pads including:
 (i) depositing the conductive material; 
 (ii) dispersing the conductive material from an initial area to a final area, the final area greater than the initial area; 
 (iii) heating the conductive material; and 
   (e) mounting an interconnect structure over the conductive material, wherein the interconnect structure is attached to the conductive material without any active treatment to the conductive material after the forming step (d).   
     
     
         8 . The method of  claim 7 , further comprising:
 (f) mounting a semiconductor package over the interconnect structure, the semiconductor package in communication with the integrated circuit device.   
     
     
         9 . The method of  claim 8 , further comprising:
 (g) forming a plurality of external interconnects on the lower surface of the substrate, the external interconnects in communication with at least one of the semiconductor package and the integrated circuit device.   
     
     
         10 . The method of  claim 7 , wherein the mounting step (c) includes mounting the integrated circuit device over the first set of contact pads, wherein the integrated circuit device is a flip chip device. 
     
     
         11 . The method of  claim 7 , wherein the depositing step (i) of the forming step (d) includes depositing the conductive material including at least one of silver (Ag), platinum (Pt), gold (Au), copper (Cu), carbon nanotube (CNT), graphene, organic metal, and mixtures thereof. 
     
     
         12 . The method of  claim 7 , wherein the forming step (d) includes forming the conductive layer over the second set of contact pads to prevent oxidation of the second set of contact pads. 
     
     
         13 . The method of  claim 7 , further comprising:
 treating the second set of contact pads with hydrophilic plasma prior to the forming step (d).   
     
     
         14 . A method comprising:
 (a) providing a substrate having an upper surface and a lower surface, the lower surface opposite the upper surface;   (b) forming first, second and third sets of contact pads on the substrate, wherein:
 the first set of contact pads is formed on the lower surface, 
 the second set of contact pads is formed on the upper surface, and 
 the third set of contact pads is formed on the upper surface, the third set of contact pads adjacent the second set of contact pads; 
   (c) mounting an integrated circuit device over the third set of contact pads;   (d) forming a first conductive material over the first set of contact pads including:
 (i) depositing the first conductive material; 
 (ii) dispersing the first conductive material from first initial area to first final area, the first final area greater than the first initial area; 
 (iii) heating the first conductive material; 
   (e) forming a second conductive material over the second set of contact pads including:
 (i) depositing the second conductive material; 
 (ii) dispersing the second conductive material from second initial area to second final area, the second final area greater than the second initial area; 
 (iii) heating the second conductive material; 
   (f) forming a plurality of external interconnects over the first conductive material, wherein the external interconnects are coupled to the first conductive material without any active treatment to the first conductive material after the forming step (d); and   (g) mounting an interconnect structure over the second conductive material, wherein the interconnect structure is attached to the second conductive material without any active treatment to the second conductive material after the forming step (e).   
     
     
         15 . The method of  claim 14 , wherein the forming step (b) includes forming the second set of contact pads about a peripheral region of the upper surface of the substrate and forming the third set of contact pads about a central region of the upper surface of the substrate. 
     
     
         16 . The method of  claim 14 , further comprising:
 forming a third conductive material over the third set of contact pads prior to the mounting step (c), the forming step including:   (i) depositing the third conductive material;   (ii) dispersing the third conductive material from third initial area to third final area, the third final area greater than the third initial area; and   (iii) heating the third conductive material.   
     
     
         17 . The method of  claim 16 , wherein the forming the third conductive material prior to the mounting step (c) and the forming step (e) can be carried out concurrently. 
     
     
         18 . The method of  claim 14 , wherein the mounting step (c) includes mounting the integrated circuit device over the third set of contact pads, wherein the integrated circuit device is a flip chip device. 
     
     
         19 . The method of  claim 14 , further comprising:
 (h) mounting a semiconductor package over the interconnect structure, the semiconductor package in communication with the integrated circuit device.   
     
     
         20 . The method of  claim 19 , wherein the forming step (f) includes forming the plurality of external interconnects over the first conductive material, the plurality of external interconnects in communication with at least one of the semiconductor package and the integrated circuit device.