Hevc video encoder and decoder for multi-core

Abstract

The disclosure provides a video encoder. The video encoder receives a frame and divides the frame into a plurality of tiles. The video encoder includes a plurality of video processing engines communicatively coupled with each other. Each video processing engine receives a tile of the plurality of tiles. A height of each tile is equal to a height of the frame and each tile comprises a plurality of rows. The plurality of video processing engines includes a first and a second video processing engine. The second video processing engine being initiated after the first video processing engines processes M rows of the plurality of rows of the tile, where M is an integer.

What is claimed is: 
     
         1 . A video encoder configured to receive a frame and configured to divide the frame into a plurality of tiles, the video encoder comprising:
 a plurality of video processing engines communicatively coupled with each other, each video processing engine configured to receive a tile of the plurality of tiles, wherein a height of each tile is equal to a height of the frame, and each tile comprises a plurality of rows; and   a first and a second video processing engine of the plurality of video processing engines, the second video processing engine being initiated after the first video processing engines processes M rows of the plurality of rows of the tile, where M is an integer.   
     
     
         2 . The video encoder of  claim 1 , wherein a width of each tile is equal to a width of the frame divided by a number of video processing engines of the plurality of video processing engines. 
     
     
         3 . The video encoder of  claim 1 , wherein in a steady state of the video encoder, the first video processing engine is configured to process a first tile and the second video processing engine processes a second tile in parallel, the first tile and the second tile are adjacent tiles of the plurality of tiles. 
     
     
         4 . The video encoder of  claim 3 , wherein the first video processing engine is configured to process M rows of the first tile before the second video processing engine is initiated to process the second tile. 
     
     
         5 . The video encoder of  claim 1 , wherein each row of the plurality of rows comprises a plurality of LCUs (largest coding units) and each LCU comprises a plurality of pixels. 
     
     
         6 . The video encoder of  claim 1 , wherein each video processing engine comprises a loop filter, the loop filter includes a work memory configured to store a set of parameters and partially filtered pixels corresponding to a set of LCUs. 
     
     
         7 . The video encoder of  claim 1  further comprising a shared memory coupled to the plurality of video processing engines. 
     
     
         8 . The video encoder of  claim 1 , wherein the work memory in each video processing engine is coupled to the shared memory. 
     
     
         9 . The video encoder of  claim 1 , wherein:
 the first video processing engine, on processing M rows of the first tile, generates a set of parameters and partially filtered pixels corresponding to a set of LCUs in the M rows of the first tile;   the set of parameters and the partially filtered pixels are stored in a work memory associated with the first video processing engine;   the set of parameters and the partially filtered pixels are provided from the work memory to the shared memory; and   the set of parameters and the partially filtered pixels are provided from the shared memory to the second video processing engine for processing the second tile.   
     
     
         10 . A method of video encoding comprising:
 receiving a plurality of frames;   dividing each frame of the plurality of frames into a plurality of tiles such that a frame comprises a plurality of tiles and a height of each tile is equal to a height of the frame, and wherein each tile comprises a plurality of rows; and   initiating a second video processing engine to process a second tile, after the first video processing engine processes M rows of a first tile, M is an integer, and wherein the first tile and the second tile are adjacent tiles of the plurality of tiles.   
     
     
         11 . The method of  claim 10  further comprising processing the first tile by the first video processing engine and the second tile by the second processing engine in parallel during a steady state. 
     
     
         12 . The method of  claim 10 , wherein processing M rows of the first tile in the first video processing engine generates a set of parameters and partially filtered pixels corresponding to a set of LCUs (largest coding units) in the M rows of the first tile, wherein each row comprises a plurality of LCUs. 
     
     
         13 . The method of  claim 10 , wherein initiating the second video processing engine further comprises activating the second video processing engine on receiving the set of parameters and the partially filtered pixels from the first video processing engine. 
     
     
         14 . The method of  claim 10 , wherein a width of each tile is equal to a width of the frame divided by a number of video processing engines in the plurality of video processing engines. 
     
     
         15 . The method of  claim 10  further comprising initiating a third video processing engine to process a third tile, after the second video processing engine processes K rows of the second tile, K is an integer, and wherein the third tile is adjacent to the second tile. 
     
     
         16 . A video decoder configured to receive a compressed bit-stream corresponding to a frame, the frame includes a plurality of tiles, the video decoder comprising:
 a plurality of video processing engines communicatively coupled with each other, each video processing engine configured to receive a compressed bit-stream corresponding to a tile of the plurality of tiles, wherein each tile comprises a plurality of rows, and wherein, a height of each tile is equal to a height of the frame and a width of each tile is equal to a width of the frame divided by a number of video processing engines in the video decoder; and   a first and a second video processing engine of the plurality of video processing engines, the second video processing engine being initiated after the first video processing engines processes compressed bit-stream corresponding to M rows of the plurality of rows of the tile, where M is an integer.   
     
     
         17 . The video decoder of  claim 16 , wherein:
 the first video processing engine is configured to process a compressed bit-stream corresponding to a first tile and the second video processing engine is configured to process a compressed bit-stream corresponding to a second tile, the first tile and the second tile are adjacent tiles of the plurality of tiles;   the first video processing engine is configured to process compressed bit-stream corresponding to M rows of the first tile and configured to generate a set of parameters and partially filtered pixels corresponding to a set of LCUs in the M rows of the first tile; and   the second video processing engine is initiated on receiving the set of parameters and partially filtered pixels from the first video processing engine.   
     
     
         18 . A computing device comprising:
 a processing unit;   a memory module coupled to the processing unit; and   a video encoder coupled to the processing unit and the memory module, the video encoder configured to receive a frame and configured to divide the frame into a plurality of tiles, the video encoder comprising:
 a plurality of video processing engines communicatively coupled with each other, each video processing engine configured to receive a tile of the plurality of tiles, wherein a height of each tile is equal to a height of the frame, and each tile comprises a plurality of rows; and 
 a first and a second video processing engine of the plurality of video processing engines, the second video processing engine being initiated after the first video processing engines processes M rows of the plurality of rows of the tile, where M is an integer. 
   
     
     
         19 . The computing device of  claim 18 , wherein processing M rows of the first tile in the first video processing engine generates a set of parameters and partially filtered pixels corresponding to a set of LCUs (largest coding unit) in the M rows of the first tile, wherein each row comprises a plurality of LCUs. 
     
     
         20 . The computing device of  claim 18 , wherein the second video processing engine is initiated on receiving the set of parameters and the partially filtered pixels from the first video processing engine.