Memory devices and methods for high random transaction rate

Abstract

A memory device can include a memory array configured to store a first plurality of bits and a second plurality of bits. The memory device may include an address port configured to receive at least a portion of a first address associated with a first command during a first clock cycle, and at least a portion of a second address associated with a second command during the first clock cycle. The memory device may include a plurality of data ports that includes a first data port configured to access the first plurality of bits in response to the receiving of the at least a portion of the first address during the first clock cycle, and a second data port configured to access the second plurality of bits in response to the receiving of the at least a portion of the second address during the first clock cycle.

What is claimed is: 
     
         1 . A device comprising:
 a memory array configured to store at least a first plurality of bits and a second plurality of bits;   an address port configured to receive at least a portion of a first address associated with a first command during a first clock cycle of a periodic timing signal, and further configured to receive at least a portion of a second address associated with a second command during the first clock cycle;   a plurality of data ports configured to transfer data into and out of the memory array, wherein the plurality of data ports includes a first data port configured to access the first plurality of bits in response to the receiving of the at least a portion of the first address during the first clock cycle, and wherein the plurality of data ports further includes a second data port configured to access the second plurality of bits in response to the receiving of the at least a portion of the second address during the first clock cycle.   
     
     
         2 . The device of  claim 1 , wherein the first clock cycle is a read clock cycle, and wherein the first data port and the second data port are configured to output read data. 
     
     
         3 . The device of  claim 1 , wherein the first clock cycle is a write clock cycle, and wherein the first data port and the second data port are configured to receive write data. 
     
     
         4 . The device of  claim 1 , wherein the first command is valid on a first edge of the first clock cycle, and wherein the second command is valid on a second edge of the first clock cycle. 
     
     
         5 . The device of  claim 1 , wherein the first address and the second address identify different and random access locations. 
     
     
         6 . The device of  claim 1 , wherein the device further comprises:
 a clock generator circuit configured to receive a clock signal, and further configured to generate the periodic timing signal based on the received clock signal; and   control logic configured to receive transaction data, and further configured to generate the first command and the second command based on the received transaction data.   
     
     
         7 . The device of  claim 1 , wherein the memory array includes a plurality of banks, wherein each bank of the plurality of banks is independently accessible by the plurality of data ports. 
     
     
         8 . The device of  claim 7 , wherein the first plurality of bits is stored in a first bank, wherein the second plurality of bits is stored in a second bank, and wherein the plurality of data ports further comprises:
 a third data port configured to access a third plurality of bits stored in a third bank, wherein the accessing of the third plurality of bits is responsive to receiving at least a portion of a third address during the first clock cycle.   
     
     
         9 . The device of  claim 1 , wherein the first data port is a first bi-directional port configured to transfer bits into and out of the memory array, and wherein the second data port is a second bi-directional port configured to transfer bits into and out of the memory array. 
     
     
         10 . The device of  claim 9 , wherein the memory array is a random access memory array configured to store the first plurality of bits in a first storage location, and further configured to store the second plurality of bits in a second storage location. 
     
     
         11 . A method comprising:
 receiving, at an address port, at least a portion of a first address associated with a first command during a first clock cycle of a periodic timing signal;   receiving, at the address port, at least a portion of a second address associated with a second command during the first clock cycle;   transferring, using a first data port of a plurality of data ports, a first plurality of data bits in response to the receiving of the at least a portion of the first address during the first clock cycle; and   transferring, using a second data port of the plurality of data ports, a second plurality of data bits in response to the receiving of the at least a portion of the second address during the first clock cycle.   
     
     
         12 . The method of  claim 11 , wherein the first clock cycle is a read clock cycle, wherein the transferring of the first plurality of data bits includes outputting first read data, and wherein the transferring of the second plurality of data bits includes outputting second read data. 
     
     
         13 . The method of  claim 11 , wherein the first clock cycle is a write clock cycle, wherein the transferring of the first plurality of data bits includes receiving first write data, and wherein the transferring of the second plurality of data bits includes receiving second write data. 
     
     
         14 . The method of  claim 11 , wherein the memory array includes a plurality of banks, wherein each bank of the plurality of banks is independently accessible by the plurality of data ports. 
     
     
         15 . The method of  claim 14 , wherein the first plurality of bits is stored in a first bank, wherein the second plurality of bits is stored in a second bank, and wherein the method further comprises:
 receiving, at the address port, at least a portion of a third address associated with a third command during the first clock cycle; and   transferring, using a third data port of the plurality of data ports, a third plurality of bits stored in a third bank in response to the receiving of the at least a portion of the third address during the first clock cycle.   
     
     
         16 . The method of  claim 11 , wherein the first address and the second address identify different and random access locations. 
     
     
         17 . A system comprising:
 a memory array configured to store at least a first plurality of bits and a second plurality of bits;   an address port configured to receive at least a portion of a first address associated with a first command during a first clock cycle of a periodic timing signal, and further configured to receive at least a portion of a second address associated with a second command during the first clock cycle;   a first data port configured to access the first plurality of bits in response to the receiving of the at least a portion of the first address during the first clock cycle; and   a second data port configured to access the second plurality of bits in response to the receiving of the at least a portion of the second address during the first clock cycle.   
     
     
         18 . The system of  claim 17 , wherein the memory array includes a plurality of banks, wherein each bank of the plurality of banks is independently accessible by a plurality of data ports that includes the first data port and the second data port. 
     
     
         19 . The system of  claim 18 , wherein the first plurality of bits is stored in a first bank, wherein the second plurality of bits is stored in a second bank, wherein the address port is further configured to receive at least a portion of a third address associated with a third command during the first clock cycle, and wherein the system further comprises:
 a third data port configured to access a third plurality of bits stored in a third bank, wherein the accessing of the third plurality of bits is responsive to receiving at least a portion of a third address during the first clock cycle.   
     
     
         20 . The system of  claim 17 , wherein the first address and the second address identify different and random access locations.