Content addressable memory system

Abstract

There is a need to highly integrate a circuit area of content addressable memory (CAM) and ensure faster operation thereof. A priority encoder and row decoder portion shares a row address register including more than one row. Each row of the row address register corresponds to each entry of a TCAM array mat and retains each address. Each row of the row address register corresponds to each word line and match line of the TCAM array mat. Writing data to the TCAM array mat activates word line for a row retained in the row address register corresponding to a specified address. Searching for the TCAM array mat activates a match line for the TCAM array mat. The row address register for the corresponding row stores the address of an entry for the TCAM array mat matching search data.

What is claimed is: 
     
         1 . A content addressable memory (CAM) comprising:
 an address register that includes a first row and a second row;   a row decoder configured to specify a first address of a first row in a data retention CAM array that is coupled to the first row of the address register, specify a second address of a second row in the data retention CAM array that is coupled to the second row of the address register, and write data to the first address and the second address in the data retention CAM array; and   a priority encoder configured to receive a first result of a comparison between data stored in the first row in the data retention CAM array and search data, receive a second result of a comparison between data stored in the second row in the data retention CAM array and the search data, and output, based on the first result and the second result, an address of a row in the data retention CAM array that matches a comparison result,   wherein the row decoder and the priority encoder are configured to share first address data stored in the first row in the address register and second address data stored in the second row in the address register, and   wherein the first row and the second row of the address register each includes CAM cells.   
     
     
         2 . The content addressable memory according to  claim 1 ,
 wherein the row decoder is configured to receive an address, compare the address as first search data with the first address data and the second address data stored in the address register, and in response to a matching comparison result, activate one word line in the data retention CAM array, and   wherein the priority encoder is configured to output one of the first address data and the second address data stored in the address register, based on an priority, in response to matching a comparison result between second search data and the first address data and a comparison result between the second search data and the second address data stored in the address register.   
     
     
         3 . The content addressable memory according to  claim 1 ,
 wherein the address register is rewritable;   wherein the content addressable memory includes a storage portion to store a recovery code that has recovered a faulty row in the data retention CAM array, and   wherein the address register is configured to accept writing of an address after fault recovery according to rewriting of the address register and based on a recovery code stored in the storage portion.   
     
     
         4 . The content addressable memory according to  claim 1 , wherein the address register includes:
 a plurality of rows including the first row and the second row; and   a plurality of sense amplifiers to amplify an output result of the priority encoder, and   wherein each sense amplifier is allocated to a specified range of rows in the address register.   
     
     
         5 . The content addressable memory according to  claim 1 ,
 wherein the address register includes a match amplifier which is a differential amplifier.   
     
     
         6 . The content addressable memory according to  claim 1 ,
 wherein the address register includes nonvolatile memory.   
     
     
         7 . The content addressable memory according to  claim 1 ,
 wherein the address register includes an FNH (force no-hit) register.   
     
     
         8 . The content addressable memory according to  claim 1 , wherein the row decoder includes:
 a recovery information data register configured to determine whether each row of the address register needs to shift an output due to faulty entry recovery; and   a recovery shift circuit configured to disable the use of a word line corresponding to a faulty row, and calculate an address for each row of the address register based on a content stored in the address register and a content stored in the recovery information data register.