Stress-resilient chip structure and dicing process

Abstract

A substrate includes a plurality of semiconductor chips arranged in a grid pattern and laterally spaced from one another by channel regions. The substrate includes a vertical stack of a semiconductor layer and at least one dielectric material layer embedding metal interconnect structures. The at least one dielectric material layer are removed along the channel regions and around vertices of the grid pattern so that each semiconductor chip includes corner surfaces that are not parallel to lines of the grid pattern. The corner surfaces can include straight surfaces or convex surfaces. The semiconductor chips are diced and subsequently bonded to a packaging substrate employing an underfill material. The corner surfaces reduce mechanical stress applied to the metal interconnect layer during the bonding process and subsequent thermal cycling processes.

What is claimed is: 
     
         1 . A semiconductor structure comprising a semiconductor chip, said semiconductor chip including a semiconductor substrate and at least one dielectric material layer that embeds metal interconnect structures, wherein said at least one dielectric material layer includes:
 pairs of parallel vertical surfaces, and   corner surfaces that are not parallel to said pairs of parallel vertical surfaces and adjoin said pairs of parallel vertical surfaces.   
     
     
         2 . The semiconductor structure of  claim 1 , wherein said semiconductor substrate has pairs of vertical semiconductor surfaces located within vertical planes of said pairs of parallel vertical surfaces of said at least one dielectric material layer, wherein said vertical semiconductor surfaces adjoin one another at vertical edges. 
     
     
         3 . The semiconductor structure of  claim 2 , further comprising a bonding substrate bonded to said semiconductor chip with an underfill material therebetween. 
     
     
         4 . The semiconductor structure of  claim 3 , wherein said bonding structure is selected from an organic package substrate, a ceramic package substrate, another semiconductor chip and a transposer. 
     
     
         5 . The semiconductor structure of  claim 3 , wherein said underfill material is in contact with said pairs of parallel vertical surfaces and said corner surfaces. 
     
     
         6 . The semiconductor structure of  claim 3 , wherein said bonding substrate is bonded to said semiconductor chip through an array of solder balls. 
     
     
         7 . The semiconductor structure of  claim 6 , wherein said array of solder balls contain at least two elements selected from tin, silver, gold, lead, zinc, bismuth, indium and copper. 
     
     
         8 . The semiconductor structure of  claim 1 , wherein said corner surfaces are planar vertical surfaces. 
     
     
         9 . The semiconductor structure of  claim 1 , wherein said corner surfaces are convex vertical surfaces. 
     
     
         10 . The semiconductor structure of  claim 1 , wherein said dielectric material layer comprises a single dielectric material. 
     
     
         11 . The semiconductor structure of  claim 1 , wherein said dielectric material comprises a plurality of different dielectric materials. 
     
     
         12 . The semiconductor structure of  claim 1 , wherein a plurality of semiconductor chip cores and inter-chip regions are contained within a vertical stack defined by said semiconductor substrate and said at least one dielectric material layer. 
     
     
         13 . The semiconductor structure of  claim 1 , wherein said plurality of semiconductor chip cores are laterally spaced by said inter-chip regions. 
     
     
         14 . The semiconductor structure of  claim 13 , wherein each semiconductor chip core has an octagonal cross sectional shape. 
     
     
         15 . The semiconductor structure of  claim 1 , further comprising an array of metallic pads located on an uppermost surface of said at least one dielectric material layer. 
     
     
         16 . The semiconductor structure of  claim 1 , wherein said at least one dielectric material layer comprises a porous dielectric material. 
     
     
         17 . The semiconductor structure of  claim 1 , wherein said at least one dielectric material layer further comprises a protective dielectric material on a surface thereof. 
     
     
         18 . The semiconductor structure of  claim 17 , wherein said protective dielectric material is selected from a polyimide resin and an epoxy resin.