Semiconductor devices including vertical channel transistors and methods of fabricating the same

Abstract

Methods of fabricating semiconductor devices may include forming first trenches in a substrate to define fin patterns and forming buried dielectric patterns filling lower regions of the first trenches. The first trenches extend in parallel. A gate dielectric layer is formed on upper inner sidewalls of the first trenches, and a gate conductive layer filling the first trenches is formed on the substrate including the gate dielectric layer. The gate conductive layer, the gate dielectric layer and the fin patterns are patterned to form second trenches crossing the first trenches and defining active pillars. Semiconductor devices may also be provided.

1 - 10 . (canceled) 
     
     
         11 . A semiconductor device, comprising:
 an active pillar protruding from a substrate;   a lower dopant region and an upper dopant region in the pillar, the lower dopant region vertically separated from the upper dopant region and separated from a first sidewall of the active pillar;   a gate electrode on a second sidewall of the active pillar; and   a gate dielectric layer between the second sidewall and the gate electrode.   
     
     
         12 . The semiconductor device as set forth in  claim 11 , further comprising:
 a buried interconnection electrically connected to the lower dopant region,   wherein a top surface of the buried interconnection is located at a lower level than a top surface of the lower dopant region.   
     
     
         13 . The semiconductor device as set forth in  claim 12 , further comprising:
 a separation dopant region between the buried interconnection and a bulk of the substrate,   wherein the separation dopant region includes at least one dopant of the same conductivity type as the lower dopant region, and the separation dopant region is connected to the lower dopant region.   
     
     
         14 . The semiconductor device as set forth in  claim 11 , further comprising:
 a void in the gate electrode; and   a void-filling dielectric pattern filling at least a portion of the void.   
     
     
         15 . The semiconductor device as set forth in  claim 11 , further comprising:
 a buried dielectric pattern between the gate electrode and the substrate, the buried dielectric pattern including an oxide.   
     
     
         16 - 19 . (canceled) 
     
     
         20 . A memory system, comprising:
 a memory device including the semiconductor device of  claim 11 ; and   a memory controller.