Gate Constructions Of Recessed Access Devices And Methods Of Forming Gate Constructions Of Recessed Access Devices

Abstract

A method of forming a gate construction of a recessed access device includes forming a pair of sidewall spacers laterally over opposing sidewalls of a gate dielectric and elevationally over first conductive gate material. The gate dielectric, the first conductive gate material, and the sidewall spacers are received within a trench formed in semiconductive material. Second conductive gate material is deposited within the semiconductive material trench between the pair of sidewall spacers in electrical connection with the first conductive gate material. Other implementations are disclosed, including recessed access device gate constructions independent of method of manufacture.

1 - 21 . (canceled) 
     
     
         22 . A method of forming recessed access device gate constructions within a memory array area and peripheral circuitry gate constructions in a peripheral circuitry area, comprising:
 forming peripheral circuitry gate dielectric and conductive peripheral circuitry gate material over a peripheral circuitry area and over a memory array area of a semiconductor substrate;   in the memory array area, etching recessed access device trenches through the conductive peripheral circuitry gate material and through the peripheral circuitry gate dielectric to within semiconductive material under the peripheral circuitry gate dielectric;   forming memory array gate dielectric over sidewalls of the semiconductive material within the trenches in the memory array area;   depositing first conductive gate material over the memory array gate dielectric within the semiconductive material trenches in the memory array area;   in the memory array area, etching the first conductive gate material to recess it within the trenches to below elevationally outermost surfaces of the semiconductive material adjacent the trenches and exposing memory array gate dielectric within the trenches;   in the memory array area, forming etched sidewall spacers that are above and below the elevationally outermost surfaces of the semiconductive material adjacent the trenches;   depositing second conductive gate material within the trenches between the etched spacers and in electrical connection with the first conductive gate material within the memory array area and over and in electrical connection with the conductive peripheral circuitry gate material in the peripheral circuitry area; and   in a single masking step, removing the second conductive gate material within the memory array area to form recessed access device gate constructions within the memory array area and removing the second conductive gate material and the conductive peripheral circuitry gate material within the peripheral circuitry area to form peripheral circuitry gate constructions.   
     
     
         23 . The method of claim  0  comprising forming an oxidation barrier over the conductive peripheral gate material in the memory array area and in the peripheral circuitry area prior to etching the trenches. 
     
     
         24 . The method of  claim 23  wherein the oxidation barrier comprises Si 3 N 4 . 
     
     
         25 . The method of  claim 23  comprising removing the oxidation barrier after the gate dielectric is formed. 
     
     
         26 . The method of  claim 25  comprising removing the oxidation barrier before forming the etched sidewall spacers. 
     
     
         27 . The method of claim  0  comprising:
 depositing the second conductive gate material elevationally over the etched spacers; and 
 patterning the second conductive gate material such that the respective conductive portions of the gate constructions are wider in cross section above and below the etched spacers than there-between. 
 
     
     
         28 . A recessed access device gate construction comprising:
 a trench within semiconductive material, the trench comprising semiconductive material sidewalls and a semiconductive material base extending between the semiconductive material sidewalls;   a gate dielectric lining over the semiconductive material trench sidewalls and the semiconductive material trench base;   blocks received within an upper portion of the trench which project laterally into the trench, the blocks being laterally thicker than thickness of the gate dielectric lining received over the trench sidewalls and trench base; and   conductive gate material received within the trench between, below, and above the blocks.   
     
     
         29 . The gate construction of  claim 28  wherein the conductive portion of the gate construction is wider in cross section above and below the blocks than there-between. 
     
     
         30 . The gate construction of  claim 27  wherein the blocks protrude above the semiconductive material in which the trench is received. 
     
     
         31 . The gate construction of  claim 30  wherein the conductive portion of the gate construction is wider in cross section above and below the blocks than there-between. 
     
     
         32 . The gate construction of  claim 28  wherein the blocks are wider at their bottoms than at their tops. 
     
     
         33 . The gate construction of  claim 28  wherein the blocks have lateral sidewall surfaces, the conductive gate material that is over the blocks having lateral sidewall surfaces that are laterally coincident with those of the blocks. 
     
     
         34 . The gate construction of  claim 33  wherein the blocks protrude above the semiconductive material in which the trench is received. 
     
     
         35 . The method of  claim 22  wherein the sidewall spacers are formed by anisotropic etching. 
     
     
         36 . The method of  claim 22  wherein the first and second conductive gate materials are of the same composition. 
     
     
         37 . The method of  claim 22  wherein the second conductive gate material is deposited into physical contact with the first conductive gate material that is within the trench.