Structure of Trench-Vertical Double Diffused MOS Transistor and Method of Forming the Same

Abstract

A structure of trench VDMOS transistor comprises an n− epi-layer/n+ substrate having trench gates formed therein, which have a trench oxide layer conformally formed and filled with a first poly-Si layer. A plurality of MOS structure formed on the mesas. Doubled diffused source regions are formed asides the MOS structure. An inter-metal dielectric layer is formed on the resulted surfaces. An interconnecting metal layer patterned as two is formed on inter-metal dielectric layer. The one is for source regions and the first poly-Si layer connection by source contact plugs and the other for the gate connection by gate contact plugs. In the other embodiment, the trenches are filled with a stack layer of a first oxide layer/a first poly-Si layer. The MOS gates with their second poly-Si layer in a form of rows are formed on the first oxide layer and the mesas. An inter-metal dielectric layer is formed on the resulted surfaces. An interconnecting metal layer is formed on the inter-metal dielectric layer and through the source contact plugs connecting the source regions and the first poly-Si layer. The drain electrode is formed on the rear surface of the n+ substrate for both embodiments.

What is claimed is: 
     
         1 . A trench vertical doubled diffused transistor (VDMOS transistor), comprising:
 a first conductive-impurity-lightly-doped epi-layer on a first conductive-impurity-heavily-doped semiconductor substrate having a plurality of trenches formed in parallel therein, said trenches spaced each other by a mesa in between and each of said trenches having a trench oxide layer formed on a bottom and sidewall and a first conductive poly-Si layer filled;   a plurality of planar gates formed on said mesas, said planar gates having a second conductive poly-Si layer on a planar gate oxide layer;   a plurality of source regions formed in said first conductive-impurity-lightly-doped epi-layer asides said planar gates, each of said source regions having doubled diffused impurities formed therein, each of said planar gates being a discrete island associated with said source regions distributed along a longitudinal direction of said trenches;   an inter-metal dielectric layer having source contact holes and gate contact holes formed therein, formed on said source regions, said first poly-Si layer, said planar gates, said inter-metal dielectric layer;   a first interconnection metal layer formed on said inter-metal dielectric layer and filled said source contact holes to form source contact plugs connecting said source regions and said first poly-Si layer;   a second interconnection metal layer formed on said inter-metal dielectric layer and filled said gate contact holes to form gate contact plugs connecting said second conductive poly-Si layer; and   a rear metal layer formed on a rear surface of said first conductive-impurity-heavily-doped semiconductor substrate as a drain electrode.   
     
     
         2 . The VDMOS transistor according to  claim 1 , wherein each of said source regions having a second conductive-impurity-implanted body formed in said first conductive-impurity-lightly-doped epi-layer, and a shallower first conductive-impurity-heavily-implanted region inside said second conductive-impurity-implanted body and said shallower first conductive-impurity-heavily-implanted region extended to a surface of said first conductive lightly doped epi-layer. 
     
     
         3 . The VDMOS transistor according to  claim 1 , wherein said source contact plugs connected said second conductive-impurity-implanted body and said first conductive-impurity-heavily-implanted region. 
     
     
         4 . The VDMOS transistor according to  claim 3 , wherein each of said source regions further comprises a second conductive-impurity-heavily-implanted region formed in said second conductive-impurity-implanted body right beneath a bottom of said source contact plugs so that said source contact plugs connected said first conductive-impurity-heavily-implanted region and said second conductive-impurity-implanted body through said second conductive-impurity-heavily-implanted region. 
     
     
         5 . The VDMOS transistor according to  claim 1 , further comprises a planar gate oxide layer formed in between said first poly-Si layer and said inter-metal dielectric layer. 
     
     
         6 . A trench vertical doubled diffused transistor (VDMOS transistor), comprising:
 a first conductive-impurity-lightly-doped epi-layer on a first conductive-impurity-heavily-doped semiconductor substrate having a plurality of trenches formed in parallel therein, said trenches spaced each other by a mesa in between and each of said trenches having a trench oxide layer formed on a bottom and sidewall, stack layers of a first oxide layer over a first conductive poly-Si layer filled in each of said trenches;   a planar gate oxide layer formed on said mesas;   a plurality of rows of a second conductive poly-Si layer formed on said planar gate oxide layer, and said first oxide layer, said rows of said second conductive poly-Si layer along a transversal direction of said trenches;   a plurality of source regions formed in said first conductive-impurity-lightly doped epi-layer asides said rows of said second poly-Si layer, each of said source regions being doubled diffused regions;   an inter-metal dielectric layer formed on said source regions, said first oxide layer, said rows of said second poly-Si layer, said inter-metal dielectric layer having source contact holes formed therein;   an interconnection metal layer formed on said inter-metal dielectric layer and filled said source contact holes to form source contact plugs connecting said source regions and said first poly-Si layer; and   a rear metal layer formed on a rear surface of said first conductive-impurity-heavily-doped semiconductor substrate as a drain electrode.   
     
     
         7 . The VDMOS transistor according to  claim 6 , wherein each of said source regions having a second conductive-impurity-implanted body formed in said first conductive-impurity-lightly-doped epi-layer, and a shallower first conductive-impurity-implanted region inside said second conductive-impurity-implanted body and said shallower first conductive-impurity-heavily-implanted region extended to a surface of said first conductive-impurity-doped epi-layer. 
     
     
         8 . The VDMOS transistor according to  claim 6 , wherein said source contact plugs connected said second conductive-impurity-implanted body and said first conductive-impurity-heavily-implanted region. 
     
     
         9 . The VDMOS transistor according to  claim 8 , wherein each of said source regions further comprises a second conductive-impurity-heavily-implanted region formed in said second conductive-impurity-implanted body right beneath a bottom of said source contact plugs so that said source contact plugs connected said first conductive-impurity-heavily-implanted region and said second conductive-impurity-implanted body through said second conductive-impurity-heavily-implanted region.