Electronic Component with Reactive Barrier and Hermetic Passivation Layer

Abstract

An electronic component is provided on a substrate. A thin-film capacitor is attached to the substrate, the thin-film capacitor includes a pyrochlore or perovskite dielectric layer between a plurality of electrode layers, the electrode layers being formed from a conductive thin-film material. A reactive barrier layer is deposited over the thin-film capacitor. The reactive barrier layer includes an oxide having an element with more than one valence state, wherein the element with more than one valence state has a molar ratio of the molar amount of the element that is in its highest valence state to its total molar amount in the barrier of 50% to 100%. Optionally layers of other materials may intervene between the capacitor and reactive barrier layer. The reactive barrier layer may be paraelectric and the electronic component may be a tunable capacitor.

What is claimed is: 
     
         1 . A method comprising:
 depositing a reactive barrier layer over a capacitor;   providing a first metal interconnect comprising an upper portion formed over a lower portion, wherein the first metal interconnect is in contact with a first electrode of the capacitor, wherein the first metal interconnect passes through the reactive barrier layer enabling a direct electrical contact for the first electrode of the capacitor; and   providing a second metal interconnect comprising an upper portion formed over a lower portion, wherein the second metal interconnect is in contact with a second electrode of the capacitor, wherein the second metal interconnect passes through the reactive barrier layer enabling a direct electrical contact for the second electrode of the capacitor.   
     
     
         2 . The method of  claim 1 , further comprising depositing a passivation layer over the reactive barrier layer, wherein the first metal interconnect passes through the passivation layer. 
     
     
         3 . The method of  claim 1 , further comprising depositing a passivation layer over the reactive barrier layer, wherein the second metal interconnect passes through the passivation layer 
     
     
         4 . The method of  claim 1 , wherein the deposition of the reactive barrier layer comprises:
 depositing the reactive barrier layer over a top surface of each of the lower portions of the first and second metal interconnects; and   subsequently etching portions of the top surfaces of the lower portions of the first and second metal interconnects thereby enabling the upper portions of the first and second metal interconnects to be formed over the lower portions of the first and second metal interconnects, respectively, wherein the etching is performed such that the reactive barrier layer covers outer portions of the top surfaces of the lower portions of the first and second metal interconnects.   
     
     
         5 . The method of  claim 1 , further comprising:
 depositing an insulating layer over the reactive barrier layer, wherein the reactive barrier layer is formed from the same dielectric material as a dielectric layer of the capacitor; and   hermetically sealing the capacitor using at least the first and second metal interconnects.   
     
     
         6 . The method of  claim 5 , wherein the insulating layer is formed from a glass dielectric material having a surface roughness of less than 0.08 micrometers. 
     
     
         7 . The method of  claim 1 , further comprising depositing a passivation layer by plasma enhanced chemical vapor deposition or low pressure chemical vapor deposition. 
     
     
         8 . The method of  claim 1 , wherein the reactive barrier layer comprises an oxide having an element with more than one valence state. 
     
     
         9 . The method of  claim 1 , wherein the reactive barrier layer comprises an oxide selected from the group consisting of: Y 2 O 3 , CeO 2 , LaO 5 , Ta 2 O 5 , TiO 2 , V 2 O 5 , PbO 2 , Mb 2 O 3 , W 2 O 5 , SnO 2 , HfO 2 , and mixtures thereof. 
     
     
         10 . The method of  claim 1 , wherein the reactive barrier layer comprises one or more of BST, PZT, PLZT, YAG, BaTiO 3 , CaTiO 3 , SrTiO 3 , BeTiO 3 , and MbTiO 3 . 
     
     
         11 . The method of  claim 1 , wherein the reactive barrier layer is a compound containing barium strontium titanium oxide and further comprising depositing a planarizing layer over the capacitor utilizing a hydrogen-free process prior to depositing the reactive barrier layer. 
     
     
         12 . The method of  claim 1 , further comprising:
 depositing an insulating layer over the reactive barrier layer.   
     
     
         13 . The method of  claim 12 , wherein the insulating layer is formed from a dielectric material. 
     
     
         14 . The method of  claim 1 , wherein the reactive barrier layer is formed from the same dielectric material as a dielectric layer of the capacitor. 
     
     
         15 . The method of  claim 1 , wherein the reactive barrier layer is paraelectric. 
     
     
         16 . The method of  claim 1 , wherein the reactive barrier layer has an average crystal diameter between 5 and 15 nanometers. 
     
     
         17 . A method comprising:
 depositing a reactive barrier layer over a capacitor;   depositing an insulating layer over the reactive barrier layer;   providing a first metal interconnect comprising an upper portion formed over a lower portion, wherein the first metal interconnect is in contact with a first electrode of the capacitor, wherein the first metal interconnect passes through the reactive barrier layer enabling a direct electrical contact for the first electrode of the capacitor; and   providing a second metal interconnect comprising an upper portion formed over a lower portion, wherein the second metal interconnect is in contact with a second electrode of the capacitor, wherein the second metal interconnect passes through the reactive barrier layer enabling a direct electrical contact for the second electrode of the capacitor.   
     
     
         18 . The method of  claim 17 , wherein the insulating layer is formed from a material having a surface roughness less than 0.08 micrometers, and wherein the deposition of the reactive barrier layer comprises:
 depositing the reactive barrier layer over a top surface of each of the lower portions of the first and second metal interconnects; and   subsequently etching portions of the top surfaces of the lower portions of the first and second metal interconnects thereby enabling the upper portions of the first and second metal interconnects to be formed over the lower portions of the first and second metal interconnects, respectively, wherein the etching is performed such that the reactive barrier layer covers outer portions of the top surfaces of the lower portions of the first and second metal interconnects.   
     
     
         19 . A method comprising:
 depositing a reactive barrier layer over the capacitor;   depositing a silicon nitride layer over the reactive barrier layer;   providing a first metal interconnect comprising an upper portion formed over a lower portion, wherein the first metal interconnect is in contact with a first electrode of the capacitor, wherein the first metal interconnect passes through the reactive barrier layer enabling a direct electrical contact for the first electrode of the capacitor; and   providing a second metal interconnect comprising an upper portion formed over a lower portion, wherein the second metal interconnect is in contact with a second electrode of the capacitor, wherein the second metal interconnect passes through the reactive barrier layer enabling a direct electrical contact for the second electrode of the capacitor.   
     
     
         20 . The method of  claim 19 , wherein the deposition of the reactive barrier layer comprises:
 depositing the reactive barrier layer over a top surface of each of the lower portions of the first and second metal interconnects; and   subsequently etching portions of the top surfaces of the lower portions of the first and second metal interconnects thereby enabling the upper portions of the first and second metal interconnects to be formed over the lower portions of the first and second metal interconnects, respectively, wherein the etching is performed such that the reactive barrier layer covers outer portions of the top surfaces of the lower portions of the first and second metal interconnects.