Semiconductor memory device and operation method thereof

Abstract

A semiconductor memory device includes a memory cell suitable for having a predetermined cell state based on a data stored therein, a control signal generation unit suitable for generating a control signal for changing the cell state of the memory cell during a reading operation, an information storage unit suitable for storing a variation status information of the control signal to which a moment when the cell state of the memory cell changes is reflected, and an output unit suitable for outputting the variation status information of the control signal stored in the information storage unit as a signal corresponding to the data stored in the memory cell.

What is claimed is: 
     
         1 . A semiconductor memory device, comprising:
 a memory cell suitable for having a predetermined cell state based on a data stored therein;   a control signal generation unit suitable for generating a control signal for changing the cell state of the memory cell during a reading operation;   an information storage unit suitable for storing a variation status information of the control signal to which a moment when the cell state of the memory cell changes is reflected; and   an output unit suitable for outputting the variation status information of the control signal stored in the information storage unit as a signal corresponding to the data stored in the memory cell.   
     
     
         2 . The semiconductor memory device of  claim 1 , wherein the variation status information of the control signal is one selected from a group comprising a voltage level of the control signal, a pulse width of the control signal, a time lapse after application of the control signal, and a number of applied pulses of the control signal. 
     
     
         3 . The semiconductor memory device of  claim 1 , wherein the cell state includes formation of a pass current of the memory cell. 
     
     
         4 . A semiconductor memory device, comprising:
 a plurality of memory cells configured in a string structure and coupled with bit lines;   a read voltage control unit suitable for changing a voltage level of a read voltage that is applied to a target memory cell to be read among the multiple memory cells;   a voltage detection unit suitable for detecting a voltage level of the bit lines based on the read voltage and generating a detection signal when a pass current is formed in the target memory cell; and   an information storage unit suitable for storing the voltage level of the read voltage in response to the detection signal.   
     
     
         5 . The semiconductor memory device of  claim 4 , further comprising a precharge unit suitable for precharging the bit lines to a predetermined voltage. 
     
     
         6 . The semiconductor memory device of  claim 4 , further comprising an output unit suitable for outputting the voltage level of the read voltage stored in the information storage unit and to which a moment when the pass current is formed is reflected as a signal corresponding to the data stored in the memory cell. 
     
     
         7 . The semiconductor memory device of  claim 4 , wherein the voltage level of the read voltage varies according to time. 
     
     
         8 . The semiconductor memory device of  claim 4 , wherein the voltage detection unit detects the pass current passing through the multiple memory cells. 
     
     
         9 . A semiconductor memory device, comprising:
 a plurality of memory cells configured in a string structure and coupled with bit lines;   a read voltage control unit suitable for changing a voltage level of a read voltage that is applied to a target memory cell to be read among the multiple memory cells;   a voltage detection unit suitable for detecting a voltage level of the bit lines based on the read voltage and generating a detection signal when a pass current is formed in the target memory cell;   a counting unit suitable for generating a count value representing a time lapse between a moment when the reading operation is enabled and a moment when the pass current is formed in the target memory cell; and   an information storage unit suitable for storing the count signal in response to the detection signal.   
     
     
         10 . The semiconductor memory device of  claim 9 , wherein the counting unit performs a counting operation from a moment when the reading operation is enabled to a moment when the detection signal is enabled. 
     
     
         11 . The semiconductor memory device of  claim 9 , further comprising a precharge unit suitable for precharging the bit lines to a predetermined voltage. 
     
     
         12 . The semiconductor memory device of  claim 9 , wherein the voltage level of the read voltage varies according to time. 
     
     
         13 . The semiconductor memory device of  claim 9 , wherein the voltage detection unit detects the pass current passing through the multiple memory cells.