Flip-flop circuit and duty ratio correction circuit using the same

Abstract

A flip-flop circuit includes a first unit configured to receive a reference clock signal and a reset signal, and a second unit configured to change an output node to a first level in response to the reference clock signal and change the output node to a second level by precharging the output node in response to a signal output from the first unit according to the reset signal.

1 . A flip-flop circuit, comprising:
 a first unit configured to receive a reference clock signal and a reset signal; and a second unit configured to change an output node to a first level in response to the reference clock signal and change the output node to a second level by precharging the output node in response to a signal output from the first unit according to the reset signal.   
     
     
         2 . The flip-flop circuit as recited in  claim 1 , further comprising a latching unit configured to latch a signal of the output node to output a signal synchronized with the reference clock signal. 
     
     
         3 . The flip-flop circuit as recited in  claim 1 , wherein a period where the output node is maintained at the first level is limited in response to an activation edge of the reset signal, and a period where the output node is precharged to the second level is limited in response to an activation edge of the reference clock signal. 
     
     
         4 . The flip-flop circuit as recited in  claim 1 , wherein the second level corresponds to a power supply voltage, and the first level corresponds to a ground voltage. 
     
     
         5 . The flip-flop circuit as recited in  claim 1 , wherein the second unit comprises:
 a first driving unit configured to drive the output node to the first level in response to the reference clock signal; and   a second driving unit configured to precharge the output node to the second level in response to the reset signal.   
     
     
         6 . The flip-flop circuit as recited in  claim 5 , wherein the first unit comprises:
 a first input unit configured to receive the reference clock signal; and   a second input unit configured to receive the reset signal to output a control signal for controlling the second driving unit.   
     
     
         7 . The flip-flop circuit as recited in  claim 6 , wherein the second unit further comprises an enabling unit configured to enable the first driving unit in response to the control signal. 
     
     
         8 . The flip-flop circuit as recited in  claim 1 , wherein the first unit comprises:
 a first MOS transistor having a source connected to a first voltage terminal, and a gate receiving the reference clock signal;   a second MOS transistor having a source connected to a drain of the first MOS transistor, and a gate receiving the reset signal; and   a third MOS transistor having a drain connected to the drain of the second MOS transistor, a source connected to a second voltage terminal, and a gate receiving the reset signal, and   the second unit comprises:   a fourth MOS transistor having a source connected to the first voltage terminal, a drain connected to the output node, and a gate connected to a common node of the second MOS transistor and the third MOS transistor;   a fifth MOS transistor having a drain connected to the output node, and a gate receiving the reference clock signal; and   a sixth MOS transistor having a drain connected to a source of the fifth MOS transistor, a source connected to the second voltage terminal, and a gate connected to the common node.   
     
     
         9 - 20 . (canceled)