Method for the formation of fin structures for finfet devices

Abstract

On a first semiconductor material substrate, an overlying sacrificial layer formed of a second semiconductor material is deposited. In a first region, a first semiconductor material region is formed over the sacrificial layer. In a second region, a second semiconductor material region is formed over the sacrificial layer. The first semiconductor material region is patterned to define a first FinFET fin. The second semiconductor material region is patterned to define a second FinFET fin. The fins are each covered with a cap and sidewall spacer. The sacrificial layer formed of the second semiconductor material is then selectively removed to form an opening below each of the first and second FinFET fins (with those fins being supported by the sidewall spacers). The openings below each of the fins are then filled with a dielectric material that serves to isolate the semiconductive materials of the fins from the substrate.

1 . A method, comprising:
 on a substrate formed of a first semiconductor material and having a first region and a second region, depositing an overlying sacrificial layer formed of a second semiconductor material;   forming for the first region a region of first semiconductor material over the sacrificial layer;   forming for the second region a region of second semiconductor material over the sacrificial layer;   patterning the region of first semiconductor material to define at least one first fin of a FinFET transistor of a first conductivity type;   patterning the region of second semiconductor material to define at least one second fin of a FinFET transistor of a second conductivity type;   covering each of the first and second fins with a cap and sidewall spacer;   selectively removing the sacrificial layer formed of the second semiconductor material to form an opening below each of the first and second fins, each first and second fin being supported by said sidewall spacer; and   filling the opening below each of the first and second fins with a dielectric material so as to isolate the first and second fins from the substrate.   
     
     
         2 . The method of  claim 1 , wherein the first semiconductor material is silicon and the second semiconductor material is silicon-germanium. 
     
     
         3 . The method of  claim 2 , wherein the FinFET transistor of the first conductivity type formed of the first semiconductor material is an n-channel device and wherein the FinFET transistor of the second conductivity type formed of the second semiconductor material is a p-channel device. 
     
     
         4 . The method of  claim 1 , wherein the substrate is a bulk semiconductor substrate. 
     
     
         5 . The method of  claim 1 , further comprising depositing an intermediate semiconductor material layer between the overlying sacrificial layer and each of the region of first semiconductor material and region of second semiconductor material. 
     
     
         6 . The method of  claim 5 , wherein the intermediate semiconductor material layer is a silicon-carbide layer. 
     
     
         7 . The method of  claim 5 , wherein each first fin comprises first semiconductor material over intermediate semiconductor material over said dielectric material, and each second fin comprises second semiconductor material over intermediate semiconductor material over said dielectric material. 
     
     
         8 . The method of  claim 1 , further comprising removing the cap and sidewall spacer to expose each of said first and second fins. 
     
     
         9 . The method of  claim 1 , wherein selectively removing the sacrificial layer formed of the second semiconductor material further forms openings adjacent each of the first and second fins, and wherein filling further comprises filling the adjacent openings with the dielectric material to separate said fins from each other. 
     
     
         10 . The method of  claim 1 , further comprising defining a trench in the substrate between adjacent fins, and wherein filling further comprises filling the trench with the dielectric material. 
     
     
         11 . The method of  claim 10 , wherein selectively removing the sacrificial layer formed of the second semiconductor material further forms openings adjacent each of the first and second fins, said trench in communication with said adjacent openings, and wherein filling further comprises filling the adjacent openings and trenches with the dielectric material. 
     
     
         12 . The method of  claim 11 , wherein covering further comprises lining each of the trenches with said sidewall spacer. 
     
     
         13 . An apparatus, comprising:
 a substrate formed of a first semiconductor material and having a first region and a second region;   in the first region, a first dielectric pedestal with a trench on opposite sides of the first dielectric pedestal;   in the second region, a second dielectric pedestal with a trench on opposite sides of the second dielectric pedestal;   in the first region, a first fin of a FinFET transistor of a first conductivity type formed of a first semiconductor material over the first dielectric pedestal and insulated from the substrate by the first dielectric pedestal; and   in the second region, a second fin of a FinFET transistor of a second conductivity type formed of a second semiconductor material over the second dielectric pedestal and insulated from the substrate by the second dielectric pedestal.   
     
     
         14 . The apparatus of  claim 13 , wherein said trenches on opposite sides of the first and second dielectric pedestals further extend into said substrate to define corresponding substrate pedestal regions supporting the dielectric pedestals. 
     
     
         15 . The apparatus of  claim 14 , further comprising a dielectric material at least partially filling each of the trenches on opposite sides of the first and second dielectric pedestals and at least partially filling each of the trenches between the substrate pedestal regions. 
     
     
         16 . The apparatus of  claim 15 , further comprising a liner in said trenches between the substrate pedestal regions and the at least partially filling dielectric material. 
     
     
         17 . The apparatus of  claim 13 , further comprising a dielectric material at least partially filling each of the trenches on opposite sides of the first and second dielectric pedestals and a liner in said trenches between the dielectric pedestals and the at least partially filling dielectric material. 
     
     
         18 . The apparatus of  claim 13 , wherein the substrate is a bulk semiconductor substrate. 
     
     
         19 . The apparatus of  claim 13 , further comprising an intermediate semiconductor material between each of the first and second dielectric pedestals and the first semiconductor material of the first fin and second semiconductor material of the second fin, respectively. 
     
     
         20 . The apparatus of  claim 19 , wherein the intermediate semiconductor material is silicon-carbide. 
     
     
         21 . The apparatus of  claim 13  wherein the first semiconductor material is silicon and the second semiconductor material is silicon-germanium. 
     
     
         22 . The apparatus of  claim 21 , wherein the FinFET transistor of the first conductivity type formed of the first semiconductor material is an n-channel device and wherein the FinFET transistor of the second conductivity type formed of the second semiconductor material is a p-channel device.