US2014353716A1PendingUtilityA1
Method of making a semiconductor device using a dummy gate
Est. expiryMay 31, 2033(~6.9 yrs left)· nominal 20-yr term from priority
H10D 84/834H10D 64/661H10D 64/018H10D 64/017H10D 62/822H10D 62/151H10D 30/6211H10D 30/797H10D 30/62H10D 30/024H10D 30/6219H01L 29/785H01L 29/6681H01L 29/66545
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Claims
Abstract
A method of making a semiconductor device includes forming a fin mask layer on a semiconductor layer, forming a dummy gate over the fin mask layer, and forming source and drain regions on opposite sides of the dummy gate. The dummy gate is removed and the underlying fin mask layer is used to define a plurality of fins in the semiconductor layer. A gate is formed over the plurality of fins.
Claims
exact text as granted — not AI-modifiedThat which is claimed is:
1 . A method of making a semiconductor device comprising:
forming a fin mask layer on a semiconductor layer; forming a dummy gate over the fin mask layer; forming source and drain regions on opposite sides of the dummy gate; removing the dummy gate and using the underlying fin mask layer to define a plurality of fins in the semiconductor layer; and forming a gate over the plurality of fins.
2 . The method according to claim 1 wherein forming the dummy gate comprises forming the dummy gate so that portions of the fin mask layer extend outwardly therefrom.
3 . The method according to claim 2 further comprising forming a dummy gate mask layer over the dummy gate.
4 . The method according to claim 3 further comprising removing the portions of the fin mask layer that extend outwardly from the dummy gate using the dummy gate mask layer.
5 . The method according to claim 1 wherein forming the dummy gate comprises forming an oxide layer and a polysilicon layer thereover.
6 . The method according to claim 1 further comprising forming sidewall spacers on the dummy gate.
7 . The method according to claim 1 further comprising removing upper portions of the semiconductor layer on opposite sides of the dummy gate to define source and drain recesses, with the source and drain regions being formed in the respective source and drain recesses.
8 . The method according to claim 1 further comprising removing the underlying fin mask layer before forming the gate.
9 . The method according to claim 1 wherein forming the source and drain regions comprises forming raised source and drain regions.
10 . The method according to claim 1 wherein forming the source and drain regions comprises forming the source and drain regions of a different material than the semiconductor layer.
11 . A method for making a semiconductor device comprising:
forming a fin mask layer on a semiconductor layer; forming a dummy gate over a portion of the fin mask layer so that portions of the fin mask layer extend outwardly therefrom; forming a dummy gate mask layer over the dummy gate; removing the portions of the fin mask layer that extend outwardly from the dummy gate using the dummy gate mask layer; removing upper portions of the semiconductor layer on opposite sides of the dummy gate to define source and drain recesses; forming source and drain regions in the source and drain recesses; removing the dummy gate mask layer and the dummy gate and using the underlying fin mask layer to define a plurality of fins in the semiconductor layer; and forming a gate over the plurality of fins.
12 . The method according to claim 11 wherein forming the dummy gate comprises forming an oxide layer and a polysilicon layer thereover.
13 . The method according to claim 11 further comprising forming sidewall spacers on the dummy gate.
14 . The method according to claim 11 further comprising removing the underlying fin mask layer before forming the gate.
15 . The method according to claim 11 wherein forming the source and drain regions comprises forming raised source and drain regions.
16 . The method according to claim 11 wherein forming the source and drain regions comprises forming the source and drain regions of a different material than the semiconductor layer.
17 . A semiconductor device comprising:
a semiconductor layer; a plurality of semiconductor fins extending upwardly from said semiconductor layer and being spaced apart along said semiconductor layer, each semiconductor fin having opposing first and second ends; a fin mask layer on said plurality of semiconductor fins; a gate overlying said plurality of semiconductor fins and said fin mask layer, and having a width aligned with the opposing first and second ends of said plurality of semiconductor fins; and source and drain regions on opposite sides of said gate.
18 . The semiconductor device according to claim 17 wherein said fin mask layer comprises a plurality of spaced apart fin mask sections, with each fin mask section on a respective semiconductor fin.
19 . The semiconductor device according to claim 17 wherein said fin mask layer comprises silicon nitride.
20 . The semiconductor device according to claim 17 wherein said source and drain regions comprise raised source and drain regions.
21 . The semiconductor device according to claim 17 wherein said source and drain regions comprise a different material than said semiconductor layer.Join the waitlist — get patent alerts
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