US2014353586A1PendingUtilityA1

Semiconductor element and method for producing the same

Assignee: SUMITOMO ELECTRIC INDUSTRIESPriority: May 31, 2013Filed: May 22, 2014Published: Dec 4, 2014
Est. expiryMay 31, 2033(~6.9 yrs left)· nominal 20-yr term from priority
H10P 74/203H10P 14/3422H10P 14/3421H10P 14/3252H10P 14/3222H10P 14/3221H10P 14/2912H10P 14/24H10F 77/1248H10F 71/127H10F 39/021H10F 77/146H01L 31/035236H01L 31/0304H01L 21/02549H01L 22/12H01L 31/184G01N 2223/615Y02E10/544G01N 23/20G01N 2223/611
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Claims

Abstract

A method for producing a semiconductor element includes a step of forming a multiple quantum well in which a GaSb layer and an InAs layer are alternately stacked on a GaSb substrate by MOVPE, wherein, in the step of forming a multiple quantum well, an InSb film is formed on at least one of a lower-surface side and an upper-surface side of the InAs layer so as to be in contact with the InAs layer.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A method for producing a semiconductor element including a III-V compound semiconductor layered body, the method comprising:
 a step of forming a multiple quantum well in which a GaSb layer and an InAs layer are alternately stacked on a GaSb substrate by metal-organic vapor phase epitaxy,   wherein, in the step of forming a multiple quantum well, an InSb film is formed on at least one of a lower-surface side and an upper-surface side of the InAs layer so as to be in contact with the InAs layer.   
     
     
         2 . The method according to  claim 1 , wherein, in the step of forming a multiple quantum well, growth of the InAs layer is followed by a first growth interruption for 3 seconds or more and 25 seconds or less, and no As source is supplied during the first growth interruption. 
     
     
         3 . The method according to  claim 2 , wherein an Sb source is supplied for partial or entire duration of the first growth interruption. 
     
     
         4 . The method according to  claim 1 , wherein a second growth interruption for 3 seconds or more and 25 seconds or less precedes growth of the InAs layer, and no Sb source is supplied during the second growth interruption. 
     
     
         5 . The method according to  claim 4 , wherein an As source is supplied for partial or entire duration of the second growth interruption. 
     
     
         6 . The method according to  claim 1 , wherein the multiple quantum well is grown with only metal-organic sources at a growth temperature of 430° C. or more and 500° C. or less. 
     
     
         7 . The method according to  claim 1 , the method further comprising, in addition to the step of forming a multiple quantum well serving as a first multiple quantum well:
 a step of forming a second multiple quantum well in which a GaSb layer and an InAs layer are alternately stacked so as to be in contact with each other, the step being performed before, after, or during the step of forming the first multiple quantum well,   wherein the second multiple quantum well does not include any InSb film on a lower-surface side or an upper-surface side of the InAs layer.   
     
     
         8 . The method according to  claim 7 , further comprising:
 a step of measuring X-ray diffraction signals for estimation of thicknesses of the layers of the first and second multiple quantum wells, the step being performed after formation of the first and second multiple quantum wells.   
     
     
         9 . A semiconductor element including III-V compound semiconductors formed on a III-V compound semiconductor substrate, the semiconductor element comprising:
 a buffer layer disposed on the substrate;   a first multiple quantum well disposed on the buffer layer, the first multiple quantum well including a GaSb layer and an InAs layer that are alternately stacked and a strain-compensating layer that is disposed on a lower-surface side or an upper-surface side of the InAs layer so as to be in contact with the InAs layer; and   a second multiple quantum well including a GaSb layer and an InAs layer that are alternately stacked so as to be in contact with each other, the second multiple quantum well not including any strain-compensating layer on a lower-surface side or an upper-surface side of the InAs layer.   
     
     
         10 . The semiconductor element according to  claim 9 , wherein the second multiple quantum well has a thickness equal to or less than a critical thickness. 
     
     
         11 . The semiconductor element according to  claim 9 , wherein the second multiple quantum well includes 4 or more and 10 or less periods of the InAs layer and the GaSb layer. 
     
     
         12 . The semiconductor element according to  claim 9 , wherein the substrate is a GaSb substrate. 
     
     
         13 . The semiconductor element according to  claim 9 , wherein the buffer layer is a GaSb layer and the substrate is formed of GaSb or a III-V compound semiconductor that is not GaSb. 
     
     
         14 . The semiconductor element according to  claim 9 , wherein the strain-compensating layer contains InSb, InAsSb, or InGaSb.

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