System and apparatus for group floating-point inflate and deflate operations

Abstract

Systems and apparatuses are presented relating a programmable processor comprising an execution unit that is operable to decode and execute instructions received from an instruction path and partition data stored in registers in the register file into multiple data elements, the execution unit capable of executing group data handling operations that re-arrange data elements in different ways in response to data handling instructions, the execution unit further capable of executing a plurality of different group floating-point and group integer arithmetic operations that each arithmetically operates on the multiple data elements stored in registers in the register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual results.

1 - 22 . (canceled) 
     
     
         23 . A programmable processor comprising:
 an instruction path;   a data path;   an external interface operable to receive data from an external source and communicate the received data over the data path;   a cache operable to retain data communicated between the external interface and the data path;   a register file operable to receive and store data from the data path and communicate the stored data to the data path; and   an execution unit coupled to the instruction path and the data path and operable to:
 decode a single instruction for selectively arranging data, specifying a data selection operand and a first and a second register each having a register width, the single instruction independently specifying the first register and the second register, the first and second registers providing a plurality of data elements each having an elemental width smaller than the register width, the data selection operand comprising a plurality of fields each selecting any one of the plurality of data elements and each field having a value not restricted by the other fields included in the data selection operand; and 
 provide in parallel the data elements selected by the fields to respective predetermined positions in a catenated result, wherein the predetermined positions are in the same order as the fields of the data selection operand. 
   
     
     
         24 . The processor of  claim 23  wherein each field of the data selection operand provides a sufficient number of bits to specify any one of the plurality of data elements. 
     
     
         25 . The processor of  claim 24  wherein each field of the data selection operand has a width of n bits, wherein the plurality of data elements comprises 2 data elements. 
     
     
         26 . The processor of  claim 23  wherein the data selection operand is provided by a register specified by the single instruction. 
     
     
         27 . The processor of  claim 26  wherein the data selection operand has a width equal to the specified register width. 
     
     
         28 . The processor of  claim 23  wherein the catenated result is provided to a register. 
     
     
         29 . The processor of  claim 23  wherein the plurality of data elements has a combined width equal to the width of the first register plus the width of the second register. 
     
     
         30 . The processor of  claim 23  wherein the instruction further specifies a data element width of the plurality of data elements. 
     
     
         31 . The processor of  claim 23  wherein each data element has a width of 8 bits. 
     
     
         32 . The processor of  claim 23  wherein the catenated result has a width of 128 bits. 
     
     
         33 . The processor of  claim 23  wherein for each field of the data selection operand, a relative location of the field within the data selection operand corresponds to a relative location of the predetermined position within the catenated result. 
     
     
         34 . The processor of  claim 23  wherein the execution unit is further operable to:
 decode a second single instruction specifying a third and a fourth register each containing a plurality of floating-point operands; 
 multiply the plurality of floating point operands in the third register by the plurality of floating-point operands in the fourth register to produce a plurality of products; and 
 provide the plurality of products to partitioned fields of a result register as a catenated result. 
 
     
     
         35 . A data processing system comprising:
 (a) a bus coupling components in the data processing system;   (b) an external memory coupled to the bus;   (c) a programmable microprocessor coupled to the bus and capable of operation independent of another host processor, the microprocessor comprising:   an instruction path;   a data path;   an external interface operable to receive data from an external source and communicate the received data over the data path;   a cache operable to retain data communicated between the external interface and the data path;   a register file operable to receive and store data from the data path and communicate the stored data to the data path; and   an execution unit coupled to the instruction path and the data path and operable to:
 decode a single instruction for selectively arranging data, specifying a data selection operand and a first and a second register each having a register width, the single instruction independently specifying the first register and the second register, the first and second registers providing a plurality of data elements each having an elemental width smaller than the register width, the data selection operand comprising a plurality of fields each selecting any one of the plurality of data elements and each field having a value not restricted by the other fields included in the data selection operand; and 
 provide in parallel the data elements selected by the fields to respective predetermined positions in a catenated result, wherein the predetermined positions are in the same order as the fields of the data selection operand. 
   
     
     
         36 . The system of  claim 35  wherein each field of the data selection operand provides a sufficient number of bits to specify any one of the plurality of data elements. 
     
     
         37 . The system of  claim 36  wherein each field of the data selection operand has a width of n bits, wherein the plurality of data elements comprises 2 data elements. 
     
     
         38 . The system of  claim 35  wherein the data selection operand is provided by a register specified by the single instruction. 
     
     
         39 . The system of  claim 38  wherein the data selection operand has a width equal to the specified register width. 
     
     
         40 . The system of  claim 35  wherein the catenated result is provided to a register. 
     
     
         41 . The system of  claim 35  wherein the plurality of data elements has a combined width equal to the width of the first register plus the width of the second register. 
     
     
         42 . The system of  claim 35  wherein the instruction further specifies a data element width of the plurality of data elements. 
     
     
         43 . The system of  claim 35  wherein each data element has a width of 8 bits. 
     
     
         44 . The system of  claim 35  wherein the catenated result has a width of 128 bits. 
     
     
         45 . The system of  claim 35  wherein for each field of the data selection operand, a relative location of the field within the data selection operand corresponds to a relative location of the predetermined position within the catenated result. 
     
     
         46 . The system of  claim 35  wherein the execution unit is further operable to:
 decode a second single instruction specifying a third and a fourth register each containing a plurality of floating-point operands; 
 multiply the plurality of floating point operands in the third register by the plurality of floating-point operands in the fourth register to produce a plurality of products; and 
 provide the plurality of products to partitioned fields of a result register as a catenated result. 
 
     
     
         47 . A programmable processor comprising:
 an instruction path;   a data path;   a plurality of registers operable to receive and store data from the data path and communicate the stored data to the data path; and   an execution unit coupled to the instruction path and the data path and operable to:
 decode a single instruction specifying a plurality of registers each having a register width, the plurality of registers independently specified by the single instruction and storing a plurality of data elements each having an elemental width smaller than the register width, an index register storing an index vector comprising a plurality of indices stored in partitioned fields of the index register and a destination register; 
   wherein each index in the index vector comprises a sufficient number of bits to represent a range of possible index values, the range of possible index values including a different index value for each of the plurality of data elements stored in the plurality of registers, allowing the index to select any data element from the plurality of data elements stored in the plurality of registers;   wherein each index in the index vector has a value not restricted by the other indices in the index vector; and
 provide in parallel the data elements selected by the indices to respective predetermined positions in the destination register, wherein the predetermined positions are in the same order as the indices stored in the partitioned fields of the index register. 
   
     
     
         48 . The processor set forth in  claim 47  wherein the plurality of registers comprises two registers. 
     
     
         49 . The processor set forth in  claim 47  wherein the number of indices stored in the index register is equal to the number of predetermined positions in the destination register. 
     
     
         50 . The processor set forth in  claim 47  wherein the index vector comprises n equal-sized indices and the destination register comprises n equal-sized predetermined positions. 
     
     
         51 . The processor set forth in  claim 50  wherein the index stored in a lowest order set of bits of the index register provides a data element to a lowest order set of bits of the destination register, the index in a second lowest order set of bits of the index register provide a data element to a second lowest order set of bits of the destination register and the index stored in a highest order set of bits of the index register provides a data element to a highest order set of bits of the destination register. 
     
     
         52 . The processor set forth in  claim 47  wherein the destination register is a 128-bit register. 
     
     
         53 . A programmable processor comprising:
 an instruction path;   a data path;   an external interface operable to receive data from an external source and communicate the received data over the data path;   a cache operable to retain data communicated between the external interface and the data path;   a plurality of registers operable to receive and store data from the data path and communicate the stored data to the data path; and   an execution unit coupled to the instruction path and the data path and operable to:
 decode a single instruction specifying a first register storing a first plurality of data elements, a second register storing a second plurality of data elements, an index register storing an index vector comprising a plurality of indices stored in partitioned fields of the index register and a destination register; 
 wherein the single instruction independently specifies the first register and the second register; 
 wherein each of the first and second registers has a register width, and each of the first and second plurality of data elements has an elemental width smaller than the register width; 
 wherein each index in the index vector comprises a sufficient number of bits to represent a range of possible index values, the range of possible index values including a different index value for each of the first and second pluralities of data elements stored in the first and second pluralities of registers, allowing the index to select any data element from the first and second pluralities of data elements stored in the first and second pluralities of registers; 
 wherein each index in the index vector has a value not restricted by the other indices in the index vector; and 
 provide in parallel data elements from the first and second pluralities of data elements selected by the indices to respective predetermined positions in the destination register, wherein the predetermined positions are in the same order as the indices stored in the partitioned fields of the index register, 
 wherein the predetermined positions are contiguous blocks of bits that take up an entire width of the destination register. 
   
     
     
         54 . The processor set forth in  claim 53  wherein the destination register is a 128-bit register. 
     
     
         55 . A data processing system comprising:
 (a) a bus coupling components in the data processing system;   (b) an external memory coupled to the bus;   (c) a programmable microprocessor coupled to the bus and capable of operation independent of another host processor, the microprocessor comprising:   an instruction path;   a data path;   an external interface operable to receive data from an external source and communicate the received data over the data path;   a cache operable to retain data communicated between the external interface and the data path;   a register file operable to receive and store data from the data path and communicate the stored data to the data path; and   an execution unit coupled to the instruction path and the data path and operable to:
 decode a single instruction specifying a plurality of registers each having a register width, the plurality of registers independently specified by the single instruction and storing a plurality of data elements each having an elemental width smaller than the register width, an index register storing an index vector comprising a plurality of indices stored in partitioned fields of the index register and a destination register; 
   wherein each index in the index vector comprises a sufficient number of bits to represent a range of possible index values, the range of possible index values including a different index value for each of the plurality of data elements stored in the plurality of registers, allowing the index to select any data element from the plurality of data elements stored in the plurality of registers;   wherein each index in the index vector has a value not restricted by the other indices in the index vector; and
 provide in parallel the data elements selected by the indices to respective predetermined positions in the destination register, wherein the predetermined positions are in the same order as the indices stored in the partitioned fields of the index register. 
   
     
     
         56 . The system set forth in  claim 55  wherein the plurality of registers comprises two registers. 
     
     
         57 . The system set forth in  claim 55  wherein the plurality of registers comprises two 64-bit registers storing a combined total of sixteen 8-bit data elements. 
     
     
         58 . The system set forth in  claim 55  wherein the number of indices stored in the index register is equal to the number of predetermined positions in the destination register. 
     
     
         59 . The system set forth in  claim 55  wherein the index vector comprises n equal-sized indices and the destination register comprises n equal-sized predetermined positions. 
     
     
         60 . The system set forth in  claim 59  wherein the index stored in a lowest order set of bits of the index register provides a data element to a lowest order set of bits of the destination register, the index in a second lowest order set of bits of the index register provide a data element to a second lowest order set of bits of the destination register and the index stored in a highest order set of bits of the index register provides a data element to a highest order set of bits of the destination register. 
     
     
         61 . The system set forth in  claim 55  wherein the destination register is a 128-bit register. 
     
     
         62 . A data processing system comprising:
 (a) a bus coupling components in the data processing system;   (b) an external memory coupled to the bus;   (c) a programmable microprocessor coupled to the bus and capable of operation independent of another host processor, the microprocessor comprising:   an instruction path;   a data path;   an external interface operable to receive data from an external source and communicate the received data over the data path;   a cache operable to retain data communicated between the external interface and the data path;   a register file operable to receive and store data from the data path and communicate the stored data to the data path; and   an execution unit coupled to the instruction path and the data path and operable to:
 decode a single instruction specifying a first register storing a first plurality of data elements, a second register storing a second plurality of data elements, an index register storing an index vector comprising a plurality of indices stored in partitioned fields of the index register and a destination register; 
 wherein the single instruction independently specifies the first register and the second register; 
 wherein each of the first and second registers has a register width, and each of the first and second plurality of data elements has an elemental width smaller than the register width; 
 wherein each index in the index vector comprises a sufficient number of bits to represent a range of possible index values, the range of possible index values including a different index value for each of the first and second pluralities of data elements stored in the first and second pluralities of registers, allowing the index to select any data element from the first and second pluralities of data elements stored in the first and second pluralities of registers; 
 wherein each index in the index vector has a value not restricted by the other indices in the index vector; and 
 provide in parallel data elements from the first and second pluralities of data elements selected by the indices to respective predetermined positions in the destination register, wherein the predetermined positions are in the same order as the indices stored in the partitioned fields of the index register, 
 wherein the predetermined positions are contiguous blocks of bits that take up an entire width of the destination register. 
   
     
     
         63 . The system set forth in  claim 62  wherein the destination register is a 128-bit register.