Methods and systems for an interposer board

Abstract

In accordance with at least some embodiments, a system includes an aggregator backplane coupled to a plurality of fans and power supplies and configured to consolidate control and monitoring for the plurality of fans and power supplies. The system also includes a plurality of compute nodes coupled to the aggregator backplane, wherein each compute node selectively communicates with the aggregator backplane via a corresponding interposer board. Each interposer board is configured to translate information passed between its corresponding compute node and the aggregator backplane.

What is claimed is: 
     
         1 . An interposer board for interfacing a compute node with an aggregator backplane of a server enclosure, the interposer board comprising:
 a printed circuit board (PCB); and   an interposer programmable interface controller (PIC) mounted on the PCB, the interposer PIC being configured to bridge a single-master serial bus topology for communications between the compute node and the interposer board with a multi-master serial bus topology for communications between the interposer board and the aggregator backplane.   
     
     
         2 . The interposer board as in  claim 1 , wherein the interposer PIC is configured to translate fan control signals from pulse width modulation (PWM) to serial bus topology data packets and to translate fan status signals from Fault to Tach fan emulation. 
     
     
         3 . The interposer board as in  claim 1 , wherein the interposer PIC is configured to manage traffic to the multi-master serial bus topology by caching fan status information, power supply status information, and power consumption meter information. 
     
     
         4 . The interposer board as in  claim 1 , wherein the interposer PIC comprises a plurality of control registers including an actual fan pulse width modulation (PWM) duty cycle register, a fan tachometer count register, and a fan fault register, and a power supply status register. 
     
     
         5 . The interposer board as in  claim 1 , further comprising a fan connector mounted on the PCB and coupled to the interposer PIC, and a single-master serial bus connector mounted to the PCB and coupled to the interposer PIC. 
     
     
         6 . A method for interfacing a plurality of compute nodes with an aggregator backplane of a multi-node server enclosure, the method comprising:
 receiving, at each of a plurality of interposer boards and via a single-master serial bus, a fan control signal from a corresponding compute node separate from the interposer board;   translating, by each such interposer board, the fan control signal received from the corresponding compute node;   selectively routing, by the interposer board, translated fan control signals to the aggregator backplane via a multi-master serial bus;   consolidating the translated fan control signals at the interposer board; and   controlling a fan based on the consolidated translated fan control signals.   
     
     
         7 . The method as in  claim 6  further comprising caching, by the interposer board, server management data from the aggregator backplane for access by the compute node. 
     
     
         8 . The method as in  claim 6 , further comprising managing a traffic level for the multi-master bus. 
     
     
         9 . The method as in  claim 6 , further comprising selectively accessing registers of an interposer board programmable interface controller (PIC) including an actual fan pulse width modulation (PWM) duty cycle register, a fan tachometer count register, and a fan fault register.