Methods of fabricating three-dimensional semiconductor memory devices using direct strapping line connections

Abstract

Memory devices include a plurality of elongate gate stacks extending in parallel on a substrate and at least one insulation region disposed in a trench between adjacent ones of the gate stacks. The at least one insulation region has linear first portions having a first width and widened second portions having a second width greater than the first width. A common source region is disposed in the substrate underlying the at least one insulation region. The devices further include respective conductive plugs passing through respective ones of the widened second portions of the at least one insulation region and electrically connected to the common source region and at least one strapping line disposed on the conductive plugs between the adjacent ones of the gate stacks and in direct contact with the conductive plugs.

What is claimed is: 
     
         1 . A method comprising:
 forming a mold stack comprising alternately arranged sacrificial layers and insulating layers on a substrate;   forming a plurality of vertical channel regions passing through the mold stack;   forming a trench passing through the mold stack between adjacent rows of the vertical channel regions and exposing a portion of the substrate, the trench having a linear first portion of a first width and a widened second portion of a second width greater than the first width;   forming a common source region in the exposed portion of the substrate;   replacing portions of the sacrificial layers exposed by the trench with conductive material to form a gate stack including alternately arranged insulating layers and gate electrode layers;   forming an insulation region that fills the first portion of the trench, partially fills the second portion of the trench and leaves a hole exposing a portion of the common source region;   forming a conductive plug in the hole and connected to the common source region;   forming a strapping line on and in direct electrical contact with the plug; and   forming a bit line electrically connected to at least some of the vertical channel regions.   
     
     
         2 . The method of  claim 1 , further comprising supplying impurities into an upper portion of the vertical channel region to form a drain region before forming of the trench. 
     
     
         3 . The method of  claim 1 , further comprising forming a common source line simultaneously with forming the bit line using a common material layer. 
     
     
         4 . The method of  claim 3 , further comprising:
 forming an interlayer dielectric on the substrate, covering the strapping line; and   forming first and second contacts passing through the interlayer dielectric and electrically contacting respective one of a vertical channel region and the strapping line.   
     
     
         5 . The method of  claim 3 , wherein the strapping line extends in parallel with the trench, and wherein the common source line and the bit line cross the strapping line. 
     
     
         6 . A method comprising:
 forming a mold stack comprising alternately arranged sacrificial layers and insulating layers on a substrate;   forming rows of vertical channel regions passing through the mold stack;   forming respective trenches in the mold stack between adjacent ones of the rows of the vertical channel regions and exposing portions of the substrate, the trenches each having linear first portions of a first width and spaced-apart widened second portions having a second width greater than the first width;   forming common source regions in the exposed portions of the substrate;   forming respective gate stacks between respective adjacent pairs of the trenches from the mold stack;   forming respective insulation regions in respective ones of the trenches, wherein portions of the insulation regions in the widened second portions of the trenches have holes therethrough that expose portions of the common source regions;   forming conductive plugs in the holes and connected to the common source regions;   forming respective strapping lines on respective ones of the insulation regions and in direct electrical contact with the plugs; and   forming a plurality of bit lines crossing the strapping lines and electrically connected to the vertical channel regions.   
     
     
         7 . The method of  claim 6 , further comprising supplying impurities into upper portions of the vertical channel regions to form drain regions before forming of the trenches. 
     
     
         8 . The method of  claim 6 , further comprising forming a common source line simultaneously with forming the bit lines using a common material layer. 
     
     
         9 . The method of  claim 8 , wherein the strapping lines extend in parallel with the trenches, and wherein the common source line and the hit lines cross the strapping lines. 
     
     
         10 . The method of  claim 6 , further comprising:
 forming an interlayer dielectric on the substrate, covering the strapping lines; and   forming contacts passing through the interlayer dielectric and electrically contacting respective ones of the vertical channel regions and the strapping lines.   
     
     
         11 . The method of  claim 6 , further comprising forming barrier layers in the second portions of the trenches before forming the plugs. 
     
     
         12 . The method of  claim 6 , wherein forming respective gate stacks between respective adjacent pairs of the trenches from the mold stack comprises replacing portions of the sacrificial layers exposed by the trenches with conductive material to form the gate stacks.