Reversible Cipher

Abstract

A cipher device having a number of data bits in an input register corresponding to a data unit element, a sudoku filter coupled with the input register, and a data selector coupled with the sudoku filter and the input register. A fob cipher device has a FPGA programmed to perform encrypting of a plaintext with a transposed Sudoku to form a first ciphertext and encrypting the first ciphertext with pseudorandom mixing bits to form a second ciphertext. A reversible encryption method includes encrypting plaintext with a transposed Sudoku forming a first ciphertext, encrypting the first ciphertext with pseudorandom mixing bits forming a second ciphertext, and outputting the plaintext-corresponding second ciphertext.

1 . A method of securing data, comprising:
 receiving a plaintext data unit;   encrypting a plaintext data unit with a transposed Sudoku to form a first ciphertext unit;   encrypting the first ciphertext unit with pseudorandom mixing bits to form a second ciphertext unit; and   outputting the second ciphertext unit corresponding to the plaintext data unit.   
     
     
         2 . The method of  claim 1  further comprising:
 receiving a third ciphertext data unit; 
 encrypting the third ciphertext data unit with a transposed Sudoku to form a fourth ciphertext unit; 
 encrypting the fourth ciphertext unit with pseudorandom mixing bits to form a second plaintext data unit; and 
 outputting the second plaintext data unit corresponding to the third ciphertext unit. 
 
     
     
         3 . A cipher device, comprising:
 an input register having a predetermined number of data bits corresponding to a data unit element;   a sudoku filter coupled with the input register having a predetermined number of elements corresponding to the predetermined number of data bits; and   a data selector coupled with the sudoku filter and the input register.   
     
     
         4 . A cipher device, comprising:
 an input port;   a FPGA coupled with the input port, and configured using an HDL to perform encrypting a plaintext data unit with a transposed Sudoku to form a first ciphertext unit and encrypting the first ciphertext unit with pseudorandom mixing bits to form a second ciphertext unit; and   an output port coupled with the FPGA;   wherein the FPGA, the input port, and the output port are configured as a FOB device, and wherein the plaintext is received at an input port and a corresponding second ciphertext unit is transmitted to the output port.   
     
     
         5 . The cipher device of  claim 4 , further comprising:
 a memory device coupled with the FPGA.   
     
     
         6 . The cipher device of  claim 4  where the input port is a USB port and the output port is a USB port 
     
     
         7 . A reversible cipher device, comprising:
 a data input register;   a transposed 10 of 16 filter coupled to the data input register; and   a 1 of 4 multiplexer having 4 data inputs coupled to the transposed 10 of 16 filter and having 2 selector inputs coupled to the data input register, wherein the cipher device is configured to produce pseudorandom bits using the 1 of 4 multiplexer and combine the pseudorandom bits with a plaintext data unit using an exclusive or function to produce a ciphertext data unit.   
     
     
         8 . The reversible cipher device of  claim 7 , wherein the ciphertext unit cannot be decrypted without an identically configured cipher device. 
     
     
         9 . The reversible cipher device of  claim 7 , further comprising:
 a process control unit (PCU) operably coupled to the data input register, the transposed 10 of 16 filter; and   a USB port coupled to the PCU.   
     
     
         10 . The reversible cipher device of  claim 9 , wherein the PCU and the USB port are configured to receive input and transmit output allowing reconfiguration, enciphering, and deciphering. 
     
     
         11 . The reversible cipher device of  claim 10 , wherein the PCU, the USB port, the data input register, the transposed 10 of 16 filter, and the 1 of 4 multiplexer are arranged on a field-programmable gate array (FPGA). 
     
     
         12 . The reversible cipher device of  claim 10 , wherein the PCU, the USB port, the data input register, the transposed 10 of 16 filter, and the 1 of 4 multiplexer are arranged in a fob device. 
     
     
         13 . The reversible cipher device of  claim 7 , further comprising a field-programmable gate array (FPGA) coupled with the data input register and the transposed 10 of 16 filter and configured using a hardware description language (HDL) to instruct the cipher device to produce the pseudorandom bits and combine the pseudorandom bits with the plaintext data unit using an exclusive or function to produce the ciphertext data unit. 
     
     
         14 . The reversible cipher device of  claim 13 , wherein the FPGA is arranged in a fob device and is coupled to an input port and an output port, wherein the plaintext is received at the input port and the ciphertext data unit is transmitted to the output port. 
     
     
         15 . The reversible cipher device of  claim 14 , wherein the input port is a USB port and the output port is a different USB port. 
     
     
         16 . The reversible cipher device of  claim 7 , further comprising a hardware description language (HDL) configured to instruct the 1 of 4 multiplexer to produce the pseudorandom bits and combine the pseudorandom bits with the plaintext data unit using an exclusive or function to produce the ciphertext data unit. 
     
     
         17 . The reversible cipher device of  claim 7 , further configured with a stream-based cipher protocol allowing the 1 of 4 multiplexer to combine the pseudorandom bits with a data stream to produce a ciphertext data stream. 
     
     
         18 . The reversible cipher device of  claim 7 , further configured to integrate a password into the ciphertext data unit, which may be used to encrypt and decrypt the plaintext data unit at a source and a destination. 
     
     
         19 . The reversible cipher device of  claim 7 , wherein the 10 of 16 filter is configured to shuffle or filter data received from the 4 data inputs into 10 preselected bit combinations. 
     
     
         20 . A cipher device, comprising:
 a data input register;   a filter coupled to the data input register and configured to shuffle or filter bits received from the data input register into preselected bit combinations, wherein the filter is configured to exclude values that may cause ignore states; and   a multiplexer having data inputs coupled to the filter and having selector inputs coupled to the data input register, wherein the cipher device is configured to produce pseudorandom bits using the multiplexer and combine the pseudorandom bits with a plaintext data unit using an exclusive or function to produce a ciphertext data unit.   
     
     
         21 . The cipher device of  claim 20 , further comprising:
 a process control unit (PCU) operably coupled to the data input register, the filter, and the multiplexer; and   a USB port coupled to the PCU.   
     
     
         22 . The cipher device of  claim 21 , wherein the filter is a 10 of 16 filter and the multiplexer is a 1 of 4 multiplexer having 4 data inputs coupled to the transposed 10 of 16 filter and having 2 selector inputs coupled to the data input register. 
     
     
         23 . The cipher device of  claim 22 , wherein the PCU, the USB port, the data input register, the transposed 10 of 16 filter, and the 1 of 4 multiplexer are arranged on a field-programmable gate array (FPGA) in a fob device. 
     
     
         24 . The cipher device of  claim 20 , further comprising a field-programmable gate array (FPGA) coupled with the multiplexer and configured using a hardware description language (HDL) to use the multiplexer to produce the pseudorandom bits and combine the pseudorandom bits with the plaintext data unit using an exclusive or function to produce the ciphertext data unit.