Cmos image sensor with noise cancellation

Abstract

A memory comprises a two dimensional array of memory cells. Each memory cell comprises a first transistor, a second transistor and a capacitor. A multi-bit datum is stored as one of a plurality of voltage signal levels driven over a vertical input signal line and further across a source and a drain of the first transistor to be stored onto a gate of the second transistor. The first transistor is selected by a horizontal WR control line. The gate of the second transistor is connected to a first terminal of the capacitor. A second terminal of the capacitor is connected to a horizontal RD control line. The RD control line is driven to couple the second transistor to drive a signal onto a vertical output signal line during a read of the stored signal on the gate.

What is claimed is: 
     
         1 . A semiconductor memory, comprising:
 a row decoder;   a plurality of memory cells, each memory cell comprising:
 a first transistor selectable by a WR line controlled by the row decoder; 
 a second transistor having a gate coupled to receive an input voltage signal from a vertical input signal line via the first transistor when the first transistor is selected; and 
 a capacitor having a first terminal connected to the gate and a second terminal connected to an RD line controlled by the row decoder, the RD line being driven to couple the gate through the capacitor to turn on the second transistor during a read of said each memory cell so that the second transistor outputs an output signal; 
   a first circuit that converts a multi-bit input datum into a multi-level input analog signal to be stored into one of the plurality of memory cells at a time; and   a second circuit that retrieves a multi-level output analog signal from one of the plurality of memory cells at a time and convert it to a digital output datum.   
     
     
         2 . A memory cell, comprising:
 a first transistor selectable by a WR input signal;   a second transistor having a gate coupled to receive an input voltage signal via the first transistor when the first transistor is selected; and   a capacitor having a first terminal connected to the gate and a second terminal connected to a RD input signal, the RD input signal being driven to couple to the gate to turn on the second transistor during a read of the memory cell in which the second transistor outputs an output signal that corresponds to a previously received input voltage signal received on the gate.   
     
     
         3 . A method for operating a memory cell that comprises a first transistor, a second transistor and a capacitor, the first transistor being connected to transmit an input signal to a gate of the second transistor, the capacitor being connected transmit another signal to the gate, comprising:
 converting a multi-bit input datum into a multi-level analog input signal;   selecting the first transistor;   transmitting the multi-level analog input signal to the gate via the first transistor;   deselecting the first transistor after the transmitting;   driving a control signal through the capacitor to the gate to turn on the second transistor;   converting a multi-level analog output signal output by the second transistor into a multi-bit output datum.