Chip package

Abstract

A chip package comprising a carrier, a chip, a plurality of first conductive elements, an encapsulation, and a conductive film is provided. The carrier has a carrying surface and a back surface opposite to the carrying surface. Furthermore, the carrier has a plurality of common contacts in the periphery of the carrying surface. The chip is disposed on the carrying surface and electrically connected to the carrier. In addition, the first conductive elements are disposed on the common contacts respectively. The encapsulation is disposed on the carrying surface and encapsulating the chip. Moreover, the conductive film is disposed over the encapsulation and the first conductive elements, so as to electrically connect with the common contacts via the first conductive elements. A process for fabricating the chip package is further provided. The chip package is capable of preventing the EMI problem and thus provides superior electrical performance.

1 .- 11 . (canceled) 
     
     
         12 . A chip package, comprising:
 a carrier, including a carrying surface and a back surface opposite to the carrying surface, the carrier further including a plurality of common contacts in the periphery of the carrying surface;   a chip, disposed on the carrying surface and electrically connected to the carrier;   a plurality of conductive elements, disposed on the common contacts respectively;   an encapsulation, disposed on the carrying surface and encapsulating the chip and the conductive elements, while a top portion of each of the conductive elements is exposed; and   a conductive film, disposed over the encapsulation and the conductive elements, so as to connect to the common contacts via the conductive elements, wherein the conductive film is directly attached to a top surface of the encapsulation and the top portions of the conductive elements.   
     
     
         13 . The chip package according to  claim 12 , wherein the conductive elements comprise a plurality of solder balls. 
     
     
         14 . The chip package according to  claim 12 , wherein the conductive film is a metal film. 
     
     
         15 . The chip package according to  claim 12 , wherein the carrier is a circuit substrate. 
     
     
         16 . The chip package according to  claim 12 , further comprising a plurality of wires connected between the chip and the carrier and encapsulated by the encapsulation. 
     
     
         17 . The chip package according to  claim 12 , further comprising a plurality of solder balls disposed on the back surface of the carrier, the solder balls being electrically connected with at least one of the chip and the conductive elements via the carrier respectively. 
     
     
         18 . The chip package according to  claim 17 , wherein a subset of the solder balls electrically connected with the chip is located in the center of the back surface of the carrier, and another subset of the solder balls electrically connected with the conductive elements is located in the periphery of the back surface of the carrier. 
     
     
         19 . A chip package, comprising:
 a carrier, including a carrying surface, a back surface opposite to the carrying surface, and a first side surface surrounding and connected between the carrying surface and the back surface, the carrier further including a plurality of common contacts at the periphery of the carrying surface;   a chip, disposed on the carrying surface and electrically connected to the carrier;   a plurality of conductive elements, disposed on and connected to the common contacts respectively;   an encapsulation, covering the carrying surface and encapsulating the chip and the conductive elements, while a top portion of each of the conductive elements is exposed; and   a conductive layer, provided with a second side surface and directly attached to a top surface of the encapsulation and the top portions of the conductive elements, wherein the first side surface of the carrier is coplanar with the second side surface of the conductive layer.   
     
     
         20 . The chip package according to  claim 19 , further comprising a peripheral device disposed adjacent to the carrying surface and electrically connected to the carrier, and the encapsulation encapsulates the peripheral device. 
     
     
         21 . The chip package according to  claim 19 , wherein the conductive elements comprise a plurality of solder balls. 
     
     
         22 . The chip package according to  claim 19 , wherein the carrier is a circuit substrate. 
     
     
         23 . The chip package according to  claim 19 , further comprising a plurality of solder balls, a subset of the solder balls electrically connected with at least one of the conductive elements and located adjacent to the periphery of the back surface of the carrier. 
     
     
         24 . A chip packaging process, comprising:
 providing a carrier which includes a carrying surface and a back surface opposite to the carrying surface, the carrier further including a plurality of common contacts in the periphery of the carrying surface;   disposing a chip on the carrying surface and electrically connecting the chip to the carrier;   forming a plurality of conductive elements on the common contacts respectively;   forming an encapsulation covering the carrying surface and encapsulating the chip and the conductive elements, the encapsulation exposing a top portion of each of the conductive elements; and   forming a conductive film on a top surface of the encapsulation so as to electrically connect the conductive film to the common contacts via the conductive elements.   
     
     
         25 . The chip packaging process according to  claim 24 , wherein forming the conductive film includes spraying a conductive material on the top surface of the encapsulation. 
     
     
         26 . The chip packaging process according to  claim 24 , wherein forming the conductive film includes spraying a conductive material on the top surface of the encapsulation and the top portions of the conductive elements. 
     
     
         27 . The chip packaging process according to  claim 24 , wherein forming the conductive elements includes forming a solder ball on each common contact respectively. 
     
     
         28 . The chip packaging process according to  claim 24 , wherein the chip is electrically connected to the carrier by flip chip bonding. 
     
     
         29 . The chip packaging process according to  claim 24 , wherein the chip is electrically connected to the carrier by wire bonding.