High voltage pmos (hvpmos) transistor with a composite drift region and manufacture method thereof
Abstract
In one embodiment, method of making a high voltage PMOS (HVPMOS) transistor, can include: (i) providing a P-type substrate; (ii) implanting N-type dopants in the P-type substrate; (iii) dispersing the implanted N-type dopants in the P-type substrate to form a deep N-type well; (iv) implanting P-type dopants of different doping concentrations in the deep N-type well along a horizontal direction of the deep N-type well; and (v) dispersing the implanted P-type dopants to form a composite drift region having an increasing doping concentration and an increasing junction depth along the horizontal direction of the deep N-type well.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A high voltage PMOS (HVPMOS) transistor, comprising:
a) a P-type substrate; b) a deep N-type well in said P-type substrate; and c) a composite drift region in said deep N-type well, wherein said composite drift region comprises an increasing doping concentration and an increasing junction depth along a horizontal direction of said deep N-type well.
2 . The HVPMOS transistor of claim 1 , further comprising a single oxide layer on said composite drift region.
3 . The HVPMOS transistor of claim 2 , further comprising:
a) a gate on a portion of said single oxide layer that corresponds to a portion of said composite drift region having a lowest doping concentration and a lowest junction depth; b) a source and a body in a portion of said deep N-type that is outside of said composite drift region; and c) a drain in a portion of said composite drift region having a highest doping concentration and a highest junction depth, wherein said drain is adjacent to said single oxide layer.
4 . The HVPMOS transistor of claim 1 , further comprising a composite oxide layer on said composite drift region, wherein said composite oxide layer comprises at least two adjacent single oxide layers along said horizontal direction of said deep N-type well.
5 . The HVPMOS transistor of claim 4 , wherein said at least two adjacent single oxide layers comprises an increasing thickness along said horizontal direction of said deep N-type well.
6 . The HVPMOS transistor of claim 5 , further comprising:
a) a gate on a portion of said composite oxide layer that corresponds to a portion of said composite drift region having a lowest doping concentration and a lowest junction depth; b) a source and a body in a portion of said deep N-type that is outside of said composite drift region; and c) a drain in a portion of said composite drift region having a highest doping concentration and a highest junction depth, wherein said drain is adjacent to said composite oxide layer.
7 . A method of making a high voltage PMOS (HVPMOS) transistor, the method comprising:
a) providing a P-type substrate; b) implanting N-type dopants in said P-type substrate; c) dispersing said implanted N-type dopants in said P-type substrate to form a deep N-type well; d) implanting P-type dopants of different doping concentrations in said deep N-type well along a horizontal direction of said deep N-type well; and e) dispersing said implanted P-type dopants to form a composite drift region having an increasing doping concentration and an increasing junction depth along said horizontal direction of said deep N-type well.
8 . The method of claim 7 , wherein said forming said composite drift region comprises:
a) implanting and dispersing, at a first time, P-type dopants in said deep N-type well to form a first drift region having a lowest doping concentration and a lowest junction depth; and b) implanting and dispersing, beginning from a side wall of said first drift region and from at a second time to an n th time in sequence, P-type dopants of increasing doping concentrations along said horizontal direction in said deep N-type well, to form adjacent second to n th drift regions having progressively increasing doping concentrations and junction depths, wherein n is an integer of at least two.
9 . The method of claim 8 , further comprising depositing oxide material on said composite drift region to form a single oxide layer.
10 . The method of claim 9 , wherein:
a) forming said single oxide layer occurs after forming said first drift region; and b) forming said single oxide layer occurs before or after forming said second drift region through said n th drift region.
11 . The method of claim 9 , further comprising:
a) forming a gate by depositing polysilicon on a portion of said single oxide layer that is on said first drift region; b) forming a source and a body contact by implanting P+ dopants and N+ dopants separately in a portion of said deep N-type well outside of said composite drift region; and c) forming a drain by implanting P+ dopants in a portion of said n th drift region adjacent to said single oxide layer.
12 . The method of claim 8 , further comprising forming a composite oxide layer by depositing oxide material on said composite drift region at least twice to form at least two adjacent single oxide layers along said horizontal direction.
13 . The method of claim 12 , wherein:
a) forming said composite oxide layer occurs after forming said first drift region; and b) forming said composite oxide layer occurs before or after forming said second drift region through said n th drift region.
14 . The method of claim 12 , wherein said at least two adjacent single oxide layers comprises an increasing thickness along said horizontal direction of said deep N-type well.
15 . The method of claim 12 , further comprising:
a) forming a gate by depositing polysilicon on a portion of said composite oxide layer that is on said first drift region; b) forming a source and a body contact by implanting P+ dopants and N+ dopants separately in a portion of said deep N-type well outside of said composite drift region; and c) forming a drain by implanting P+ dopants in a portion of said n th drift region adjacent to said composite oxide layer.Join the waitlist — get patent alerts
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