US2014338958A1PendingUtilityA1
Printed circuit board and method of manufacturing the same
Est. expiryJul 17, 2029(~3 yrs left)· nominal 20-yr term from priority
H05K 2201/0191H05K 3/242C25D 7/00H05K 2201/0187H05K 2201/10977H05K 1/056Y10T29/49126Y10T29/49124H05K 3/28H05K 3/002H05K 3/0052
57
PatentIndex Score
0
Cited by
0
References
0
Claims
Abstract
A base insulating layer is formed on a suspension body. A lead wire for plating and a wiring trace are integrally formed on the base insulating layer. A cover insulating layer is formed on the base insulating layer to cover the lead wire for plating and the wiring trace. A thickness of a portion of the cover insulating layer above a region of the base insulating layer in which the lead wire for plating is formed is set smaller than the thickness of a portion of the cover insulating layer above other regions of the base insulating layer.
Claims
exact text as granted — not AI-modifiedI/We claim:
1 . A printed circuit board comprising:
a first insulating layer; a wiring trace formed on said first insulating layer; a terminal provided at a portion of said wiring trace; a lead for plating formed on said first insulating layer to extend from said wiring trace; and a second insulating layer formed on said first insulating layer to cover said wiring trace excluding said terminal and not to cover at least a portion of said lead for plating, wherein an effective dielectric constant of a region overlapping said lead for plating is set smaller than an effective dielectric constant of a region overlapping said wiring trace.
2 . The printed circuit board according to claim 1 , wherein one or a plurality of openings are formed in a portion of said second insulating layer overlapping said lead for plating such that said second insulating layer covers a portion of said lead for plating.
3 . The printed circuit board according to claim 2 , wherein a thickness of the portion of said second insulating layer overlapping said lead for plating is set smaller than a thickness of the portion of said second insulating layer overlapping said wiring trace.
4 . The printed circuit board according to claim 2 , wherein said plurality of openings are formed to have a mesh-like pattern at the portion of said second insulating layer overlapping said lead for plating.
5 . The printed circuit board according to claim 2 , wherein said one or plurality of openings are formed to have a slit-like shape.
6 . The printed circuit board according to claim 2 , wherein a material having a lower dielectric constant than a dielectric constant of said second insulating layer is filled in said one or plurality of openings.
7 . The printed circuit board according to claim 1 , wherein said second insulating layer is formed not to cover said lead for plating.
8 . A method of manufacturing a printed circuit board, comprising the steps of:
forming a conductor pattern including a wiring trace, a terminal provided at a portion of said wiring trace, and a lead for plating extending from said wiring trace on a first insulating layer; forming a second insulating layer on said first insulating layer to cover said wiring trace excluding said terminal and cover said lead for plating; forming the terminal coated with a plating layer at the portion of said wiring trace by feeding power to said wiring trace through said lead for plating; and forming an opening at a portion of either said first insulating layer or said second insulating layer overlapping said lead for plating such that an effective dielectric constant of a region overlapping said lead for plating is smaller than an effective dielectric constant of a region overlapping said wiring trace.
9 . The method of manufacturing the printed circuit board according to claim 8 , further comprising the step of filling a material having a lower dielectric constant than a dielectric constant of said first or second insulating layer in said opening formed at the portion of either said first insulating layer or said second insulating layer overlapping said lead for plating.Join the waitlist — get patent alerts
Track US2014338958A1 — get alerts on status changes and closely related new filings.
We store only your email — no account needed. See our privacy policy.