US2014334231A1PendingUtilityA1
Nonvolatile semiconductor memory device and method for erasing data thereof
Est. expiryJun 14, 2031(~4.8 yrs left)· nominal 20-yr term from priority
G11C 16/16G11C 16/26G11C 16/0483G11C 16/10G11C 16/08G11C 2213/71H10D 30/693H10B 43/27
45
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Claims
Abstract
A control circuit is configured to set a drain-side select transistor and a source-side select transistor connected to a selected memory string to non-conductive states. The control circuit is configured to apply a first voltage to a non-selected word line connected to a gate of a non-selected memory cell in the selected memory string. The control circuit is configured to apply a second voltage to a selected word line connected to a gate of a selected memory cell in the selected memory string. The second voltage is smaller than the first voltage in an erasing operation.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A nonvolatile semiconductor memory device comprising:
a semiconductor substrate; a memory cell array comprising a memory string including a plurality of memory cells, the memory cells being stacked on the semiconductor substrate; a plurality of word lines connected to the plurality of memory cells; a bit line electrically connected to one end of the memory string; a source line electrically connected to the other end of the memory string; a drain-side select transistor provided between one end of the memory string and the bit line; a source-side select transistor provided between the other end of the memory string and the source line; and a control circuit configured to control voltages to be applied to the memory string, the plurality of word lines, the bit line, and the source line, and the control circuit being configured to set the drain-side select transistor and the source-side select transistor connected to a selected memory string to non-conductive states, the control circuit being configured to apply a first voltage to a non-selected word line connected to a gate of a non-selected memory cell in the selected memory string, the control circuit being configured to apply a second voltage to a selected word line connected to a gate of a selected memory cell in the selected memory string, the second voltage being smaller than the first voltage in an erasing operation.Join the waitlist — get patent alerts
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