Managing clock and recovery data

Abstract

Disclosed are various embodiments for a clock and data recovery (CDR) system. The CDR system comprises a transition detection stage and a clock recovery stage. The transition detection stage is responsible for receiving the data signal and detecting whether a transition exists in the data signal by oversampling the data signal. The clock recovery stage generates a recovery clock based on whether there is a transition in the data signal.

1 . A method, comprising:
 receiving a data signal, the data signal being received without receiving a timing reference for the data signal, wherein the data signal is associated with an original clock period;   generating an internal reference clock, wherein a clock period of the internal reference clock is less than the original clock period according to a factor amount;   detecting a transition in the data signal by sampling the data signal according to the internal reference clock;   sampling the data signal according to the internal reference clock to generate a recovery data signal; and   in response to the transition being detected, generating a recovery clock for the recovery data signal.   
     
     
         2 . The method of  claim 1 , wherein detecting the transition in the data signal by sampling the data signal according to the internal reference clock comprises detecting a difference between a first sample of the data signal and a second sample of the data signal. 
     
     
         3 . The method of  claim 2 , wherein at least one of the first sample of the data signal or the second sample of the data signal is generated by a sequential logic element. 
     
     
         4 . The method of  claim 1 , wherein generating the recovery clock for the recovery data signal comprises using a first stage sequential logic element to generate a first stage output signal in response to detecting the transition. 
     
     
         5 . The method of  claim 4 , wherein generating the recovery clock for the recovery data signal further comprises using a second stage sequential logic element to generate a second stage output signal in response to detecting the transition. 
     
     
         6 . The method of  claim 5 , wherein generating the recovery clock for the recovery data signal further comprises detecting a difference between the first stage output signal and the second stage output signal to generate a phase detection signal. 
     
     
         7 . The method of  claim 6 , wherein an input of the second stage sequential logic element is responsive to the transition and the phase detection signal. 
     
     
         8 . A system comprising:
 a clock and data recovery (CDR) circuit operable to
 receive a data signal, wherein the data signal is associated with an original clock period; 
 receive an internal reference clock, wherein a clock period of the internal reference clock is less than the original clock period according to a factor amount; 
 sample the data signal according to the internal reference clock to generate a recovery data signal; and 
 generate a recovery clock for the recovery data signal by detecting a difference between a first sample of the data signal and a second sample of the data signal. 
   
     
     
         9 . The system of  claim 8 , wherein the factor amount is equal to four, wherein the clock period of the internal reference clock is substantially four times shorter than the original clock period. 
     
     
         10 . The system of  claim 8 , wherein the CDR circuit comprises a plurality of cascaded flip-flops that are operable to reduce a metastability in the data signal. 
     
     
         11 . The system of  claim 8 , wherein the CDR circuit comprises a first stage sequential logic element operable to generate a first stage output signal, the first stage output signal being based on the difference between the first sample of the data signal and the second sample of the data signal. 
     
     
         12 . The system of  claim 11 , wherein the CDR circuit comprises a second stage sequential logic element operable to generate a second stage output signal, the second stage output signal being based on the difference between the first sample of the data signal and the second sample of the data signal. 
     
     
         13 . The system of  claim 12 , wherein the CDR is further operable to generate the recovery clock by detecting a difference between the first stage output signal and the second stage output signal. 
     
     
         14 . A clock and data recovery (CDR) circuit comprising:
 a transition detection stage comprises
 circuitry that receives a data signal, wherein the data signal is associated with an original clock period; and 
 circuitry that generates a phase reset signal based on sampling the data signal according to an internal reference clock, the phase reset signal indicating a transition in the data signal, wherein a clock period of the internal reference clock is less than the original clock period according to a factor amount; 
 a clock recovery stage comprising circuitry that generates a recovery clock using the phase reset signal. 
   
     
     
         15 . The system of  claim 14 , wherein the factor amount is a power of two, the factor amount being greater than two. 
     
     
         16 . The system of  claim 14 , wherein the transition detection stage comprises a plurality of cascaded sequential logic elements operable to reduce a metastability in the data signal. 
     
     
         17 . The system of  claim 14 , wherein the clock recovery stage comprises:
 a first stage sequential logic element operable to generate a first stage output signal using the phase reset signal; and   a second stage sequential logic element operable to generate a second stage output signal using the phase reset signal.   
     
     
         18 . The system of  claim 17 , wherein an input of the first stage sequential logic element comprises a feedback loop using the first stage output signal. 
     
     
         19 . The system of  claim 17 , wherein an input of the second stage sequential logic element is generated by detecting a difference between the first stage output signal and the second stage output signal. 
     
     
         20 . The system of  claim 17 , wherein the first stage sequential logic element comprises a first flip-flop that is operable to receive the internal reference clock, wherein the second stage sequential logic element comprises a second flip-flop that is operable to receive the internal reference clock.