High voltage gate formation

Abstract

Embodiments described herein generally relate to methods of manufacturing charge-trapping memory by patterning the high voltage gates before other gates are formed. One advantage of such an approach is that a thin poly layer may be used to form memory and low voltage gates while protecting high voltage gates from implant penetration. One approach to accomplishing this is to dispose the layer of poly, and then dispose a mask and a thick resist to pattern the high voltage gates. In this manner, the high voltage gates are formed before either the low voltage gates or the memory cells.

What is claimed is: 
     
         1 . A semiconductor device having a memory region, a first substrate region, and a second substrate region, the semiconductor device comprising:
 first gates in the first substrate region;   second gates in the second substrate region;   third gates in the memory region; and   fourth gates in the memory region, wherein each fourth gate is formed adjacent to a corresponding third gate, and wherein a sidewall of each of the fourth gates is formed before one or more sidewalls of the second gates.   
     
     
         2 . The semiconductor device of  claim 1 , wherein one or more sidewalls of the first gates are formed before one or more sidewalls of the second gates and one or more sidewalls of the fourth gates. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the second gates have a same thickness, but a different width, than the first gates. 
     
     
         4 . The semiconductor device of  claim 1 , further comprising a trench between the first substrate region and the second substrate region. 
     
     
         5 . The semiconductor device of  claim 1 , further comprising a lightly doped section in the first substrate region, adjacent to the first gates. 
     
     
         6 . The semiconductor device of  claim 1 , wherein the first substrate region is a high voltage substrate region and the second substrate region is a low voltage substrate region. 
     
     
         7 . The semiconductor device of  claim 1 , wherein the memory region comprises a charge trapping dielectric at least one of under and adjacent to the sidewall of each of the fourth gates. 
     
     
         8 . The semiconductor device of  claim 1 , wherein a gate length of the first gates is at least twice as long as a gate length of the second gates. 
     
     
         9 . The semiconductor device of  claim 1 , further comprising a layer of nitride sandwiched between layers of oxide and adjacent to the fourth gates. 
     
     
         10 . The semiconductor device of  claim 1 , further comprising a partially etched trench.