Asymmetric mesh noc topologies

Abstract

A method of interconnecting blocks of heterogeneous dimensions using a NoC interconnect with sparse mesh topology includes determining a size of a mesh reference grid based on dimensions of the chip, dimensions of the blocks of heterogeneous dimensions, relative placement of the blocks and a number of host ports required for each of the blocks of heterogeneous dimensions, overlaying the blocks of heterogeneous dimensions on the mesh reference grid based on based on a guidance floor plan for placement of the blocks of heterogeneous dimensions, removing ones of a plurality of nodes and corresponding ones of links to the ones of the plurality of nodes which are blocked by the overlaid blocks of heterogeneous dimensions, based on porosity information of the blocks of heterogeneous dimensions, and mapping inter-block communication of the network-on-chip architecture over remaining ones of the nodes and corresponding remaining ones of the links

What is claimed is: 
     
         1 - 22 . (canceled) 
     
     
         23 . A system on chip, comprising:
 a plurality of blocks of substantially non-uniform shapes and dimensions;   a plurality of routers; and   a plurality of links between routers,   wherein the plurality of blocks and the plurality of routers are interconnected by the plurality of links using a Network-on-Chip architecture with a sparse mesh topology, and   wherein the sparse mesh topology comprises a sparsely populated mesh which is a subset of a full mesh having one or more of the plurality of routers or links removed, and   wherein the plurality of blocks communicate among each other by routing messages over the remaining ones of the plurality of routers and links of the sparse mesh.