QFN/SON-Compatible Package

Abstract

A leadless package and method for manufacturing silicon based leadless QFN/SON compatible packages are described. In addition the package allows for hermetic sealing of devices while maintaining electrical and optical access. Micro-vias with feed-through metallization through a silicon structure facilitates a surface mount technology compatible silicon package with bottom SMT pads and top surface device integration. Sloped edges on the SMT side enable solder filleting for post solder inspection. Hermetic seal can be attained for example using anodic bonding of a glass lid or using metal soldering. Metal soldering enables the use of solder bumps to provide electrical connections for the package to the lid with integrated device functionality used for sealing. Hermetically sealed silicon packages eliminates the need for an extra packaging layer required in plastic packages and provides a standard interface for enclosing one or more discrete devices.

What is claimed is: 
     
         1 . A method of manufacturing a leadless package for integrated circuits and micro-components, wherein the method comprises:
 disposing a plurality of surface mounting technology (SMT) land pads on a bottom surface of a silicon structure, the SMT land pads configured to provide electrical connections to a substrate;   providing a concave surface on a top surface of the silicon structure, the concave surface defining a cavity configured to envelop one or more discrete devices;   disposing a plurality of electrical contacts on the top surface, the electrical contacts configured to provide electrical connections to the one or more devices in the cavity;   creating a plurality of micro-vias configured to extend from the SMT land pads on the bottom surface to the electrical contacts in the cavity of the top surface;   providing sloped edges on the bottom surface, the sloped edges configured to facilitate solder filleting on the SMT land pads for a post soldering inspection;   providing feed-through metallization through the micro-vias, the feed-through metallization configured to form electrical connections from the SMT land pads on the bottom surface through the silicon structure to the electrical contacts on the top surface; and   disposing a silicon lid on the top surface of the structure to provide a hermetic seal.   
     
     
         2 . The method of  claim 1  wherein disposing the silicon lid further comprises disposing a metal soldering ring on the top surface, the metal soldering ring configured to provide the hermetic seal. 
     
     
         3 . The method of  claim 1  wherein disposing the silicon lid further comprises disposing a plurality of metal solder pads configured to provide electrical contacts between the silicon structure and the lid. 
     
     
         4 . The method of  claim 1  wherein:
 providing the concave surface to define the cavity comprises providing sloped sidewalls; and 
 disposing the silicon lid further comprises disposing metallization on the sloped cavity sidewalls for shielding or reflection. 
 
     
     
         5 . The method of  claim 1  wherein disposing the silicon lid further comprises using anodic bonding to provide the hermetic seal. 
     
     
         6 . The method of  claim 5  wherein disposing the silicon lid further comprises disposing a transparent lid configured to allow light to pass through the transparent lid. 
     
     
         7 . The method of  claim 1  wherein disposing the electrical contacts comprises disposing wire bond pads configured to provide electrical connections to the one or more devices using wire bonds. 
     
     
         8 . The method of  claim 1  further comprising providing a layout of the SMT land pads that complies with quad flatpack-no lead/small outline-no lead (QFN/SON) layout rules. 
     
     
         9 . The method of  claim 1  wherein disposing the electrical contacts comprises disposing dedicated contact layouts configured to provide electrical connection to the one or more devices using flip-chip bonds. 
     
     
         10 . The method of  claim 1  further comprising:
 disposing a plurality of solder bumps on the top surface, the solder bumps configured to electrically connect the lid and the silicon structure; and 
 disposing on the lid a second device configured to electrically connect to the solder bumps. 
 
     
     
         11 . The method of  claim 1  wherein providing the feed-through metallization through the micro-vias further comprises using a dry or wet etching technique. 
     
     
         12 . The method of  claim 1  further comprising forming a plurality of sloped side edges on the bottom surface of the silicon structure, the sloped side edges configured to extend therein electrical connections to the SMT land pads. 
     
     
         13 . The method of  claim 12  wherein forming the sloped side edges further comprises using wet etching to obtain a slope angle of about 54.7 degrees. 
     
     
         14 . A method comprising:
 forming a surface mounting technology (SMT) land pad on a bottom surface of a silicon structure, wherein the SMT land pad extends directly on a sloped side edge of the bottom surface toward a top surface of the silicon structure;   forming feed-through metallization through a via extending from the SMT land pad on the bottom surface to the top surface of the silicon structure; and   forming an electrical contact on the top surface of the structure.   
     
     
         15 . The method of  claim 14 , further comprising removing a portion of the top surface of the silicon structure to form a cavity therein. 
     
     
         16 . The method of  claim 15 , wherein forming the electrical contact on the top surface of the structure includes forming the electrical contact within the cavity. 
     
     
         17 . The method of  claim 14 , further comprising forming the via by performing an etching process to remove a portion of the silicon structure. 
     
     
         18 . The method of  claim 17 , wherein forming the via by performing the etching process includes forming the sloped slide edge of the bottom surface by performing the etching process to remove another portion of the silicon structure. 
     
     
         19 . The method of  claim 15 , further comprising:
 positioning a device within the cavity such that the device is in electrical communication with the electrical contact; and   positioning a lid over the top surface of the silicon structure to seal the device within the cavity.   
     
     
         20 . A method of manufacturing a leadless package for integrated circuits and micro- components, wherein the method comprises:
 disposing a metallization layout on a silicon structure;   hermetically sealing a lid onto the silicon structure using metal soldering or anodic bonding, wherein the hermetic seal is achieved in a single leadless package;   providing a plurality of sloped edges on a SMT side of the silicon structure; and   disposing a plurality of electrical contacts extending to the sloped edges, wherein the sloped edges are configured to facilitate solder filleting on the electrical contacts extending to the sloped edges.