Semiconductor device, control method thereof and data processing system

Abstract

Disclosed herein is a semiconductor device comprising a global bit line, a first local bit line coupled to normal memory cells, a second local bit line coupled to redundant memory cells first and second hierarchical switches, a precharge circuit precharging the global bit line, a redundancy determination circuit determining whether or not an accessed address matches a defective address, and a control circuit. In a standby state, the global bit line and the second local bit line are precharged through the second hierarchical switch. In an active state, the first local bit line is precharged through the first hierarchical switch, subsequently when the redundancy determination circuit determines that the addresses do not match, the second hierarchical switch is inactivated to access the normal memory cells, and when the redundancy determination circuit determines that the addresses match each other, the first hierarchical switch is inactivated to access the redundant memory cells.

1 . A method for operating a semiconductor device, the method comprising:
 inactivating a first switch that electrically connects the global bit line and a first local bit line corresponding to normal memory cells, and activating a second switch that electrically connects the global bit line and a second local bit line corresponding to redundant memory cells usable for replacing normal memory cells;   precharging a global bit line to a predetermined voltage;   activating the first switch to connect the first local bit line to the global bit line;   determining whether a normal memory cell to be accessed is to be replaced with a corresponding redundant memory cell;   inactivating the first switch when the determination indicates that a replacement of the normal memory cell is performed and accessing the redundant memory cell; and   maintaining the first switch in the active state, inactivating the second switch that has been active when the replacement is not performed, and accessing the normal memory cell.   
     
     
         2 . The method according to  claim 1 , further comprising maintaining the second switch in the active state while the determination is made. 
     
     
         3 . The method according to  claim 2 , further comprising maintaining the second switch in the active state when the replacement is performed. 
     
     
         4 . The method according to  claim 1 , wherein the first switch is activated during a period in which the determination is being made as to whether the normal memory cell to be accessed is to be replaced with the corresponding redundant memory cell. 
     
     
         5 . The method according to  claim 4 , wherein by activating the first switch, the first local bit line is precharged to the predetermined voltage by the time the determination is made. 
     
     
         6 . The method according to  claim 5 , wherein the precharging of the first local bit line occurs in parallel with making the determination. 
     
     
         7 . The method according to  claim 1 , wherein the determination is made by comparing a row address corresponding to the normal memory cell to be accessed to a defective address using a redundancy determination circuit. 
     
     
         8 . The method according to  claim 1 , wherein activating the second switch precharges the second local bit line to the predetermined voltage. 
     
     
         9 . The method according to  claim 1 , further comprising:
 when accessing other normal memory cells corresponding to the second local bit line, maintaining the first switch in an inactive state and maintaining the second switch in an active state regardless of whether the determination has been made; and   accessing the other normal memory cells or the redundant memory cells instead of accessing the normal memory cells.   
     
     
         10 . The method according to  claim 1 , further comprising:
 activating a word line corresponding to the normal memory cells if the replacement is not performed; and   activating a redundant word line corresponding to the redundant memory cell if the replacement is performed.   
     
     
         11 . A method for operating a semiconductor device having a memory array comprising:
 holding a first local bit line corresponding to normal memory cells of the memory array in a floating state by deactivating a first hierarchical switch between the first local bit line and the global bit line;   precharging a global bit line to a predetermined voltage;   precharging a second local bit line corresponding redundant memory cells of the memory array to the predetermined voltage by activating a second hierarchical switch between the second local bit line and the global bit line;   in response to receiving a request to access a normal memory cell, determining whether the normal memory cell is to be replaced with a redundant memory cell while concurrently precharging the first local bit line to the predetermined voltage by activating the first hierarchical switch;   accessing the normal memory cell if a replacement is not made; and   accessing the replacement memory cell if the replacement is made.   
     
     
         12 . The method of  claim 11 , comprising, after precharging the first local bit line by activating the first hierarchical switch, deactivating the second hierarchical switch and disconnecting the second local bit line from the global bit line if it is determined that the replacement is not to be made. 
     
     
         13 . The method of  claim 11 , comprising, after precharging the first local bit line by activating the first hierarchical switch, deactivating the first hierarchical switch if it is determined that the replacement is to be made. 
     
     
         14 . The method of  claim 11 , wherein the first local bit line and the second local bit line do not include corresponding precharging circuits separate from the first and second hierarchical switches. 
     
     
         15 . The method of  claim 11 , wherein the determination of whether a replacement is to be made is indicated by a signal generated by a redundancy determination circuit that compares an address in the received request to one or more defective addresses. 
     
     
         16 . The method of  claim 15 , comprising outputting the signal to a row decoder, a memory mat control unit, and a switch control unit of the semiconductor device.