Semiconductor devices and methods of manufacturing the same

Abstract

Provided are a semiconductor device, which can facilitate a salicide process and can prevent a gate from being damaged due to misalign, and a method of manufacturing of the semiconductor device. The method includes forming a first insulation layer pattern on a substrate having a gate pattern and a source/drain region formed at both sides of the gate pattern, the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source/drain region, forming a second insulation layer on the entire surface of the substrate to cover the first insulation layer pattern and the silicide layer, and forming a contact hole in the second insulation layer to expose the silicide layer.

What is claimed is: 
     
         1 . A method of manufacturing a semiconductor device, the method comprising:
 forming, on a substrate, a source/drain region on substantially opposing sides of a gate pattern that is on the substrate;   forming a first insulation layer pattern on the substrate, the first insulation layer pattern including an exposed portion of the source/drain region;   forming a silicide layer on the exposed portions of the source/drain region by depositing at least one metal layer on the exposed portion of the source/drain region to react with the source/drain region;   forming a second insulation layer on the surface of the substrate to cover the first insulation layer pattern and the silicide layer;   forming a contact hole in the second insulation layer by etching the second insulation layer to expose the silicide layer; and   forming a metal wire contact by filling the contact hole with conductive material.   
     
     
         2 . The method according to  claim 1 , wherein an aspect ratio of the source/drain region to the gate pattern is about 3:1 or less. 
     
     
         3 . The method according to  claim 1 , wherein a step difference between the source/drain region and the gate pattern is about 250 Å or less from the substrate. 
     
     
         4 . The method according to  claim 1 , wherein the source/drain region and the gate pattern are positioned at substantially a same height from the substrate. 
     
     
         5 . The method according to  claim 1 , wherein the gate electrode is formed of a metal containing material. 
     
     
         6 . The method according to  claim 1 , wherein the first insulation layer pattern includes a first material and the second insulation layer includes a second material that is different from the first material. 
     
     
         7 . The method according to  claim 1 , wherein the first insulation layer pattern is formed of SiN. 
     
     
         8 . The method according to  claim 1 , wherein the second insulation layer is formed of silicon oxide. 
     
     
         9 . The method according to  claim 1 , wherein the source/drain region is formed by implanting n- or p-type impurity ions through epitaxial growth. 
     
     
         10 . The method according to  claim 1 , wherein forming the silicide layer on the exposed portions of the source/drain region comprises reacting the metal layer with silicon of the source/drain region. 
     
     
         11 . The method according to  claim 1 , wherein the source/drain region is formed by epitaxially growing a silicon germanium layer in a trench formed by etching a predetermined region of the substrate. 
     
     
         12 . The method according to  claim 11 , wherein the trench has a hexagonal profile. 
     
     
         13 . The method according to  claim 11 , wherein the trench includes a tip having a maximum width that is aligned with sidewalls of the gate pattern.