Photolithographic, thickness non-uniformity, compensation features for optical photolithographic semiconductor structure formation

Abstract

A semiconductor structure having a substrate; an active device formed in an active semiconductor region of the substrate, the active device having a control electrode for controlling a flow of carriers through the active semiconductor region between a pair of electrical contacts; and a photolithographic, thickness non-uniformity, compensation feature, disposed on the surface substrate off of the active semiconductor region. In one embodiment the feature comprises pads on the surface of the substrate and off of the active semiconductor region.

What is claimed is: 
     
         1 . A semiconductor structure, comprising:
 a substrate having an inactive region and an adjacent active semiconductor region;   an active device formed in the active semiconductor region of the substrate, the active device having a control electrode for controlling a flow of carriers through the active semiconductor region between a pair of electrical contacts; and   a photolithographic, thickness non-uniformity, compensation feature, disposed on the surface substrate on the inactive region.   
     
     
         2 . The semiconductor structure recited in  claim 1  wherein the feature comprises pads on the surface of the substrate and on the inactive region. 
     
     
         3 . The semiconductor structure recited in  claim 1  wherein the feature comprises two pair of pads on opposite sides of the active semiconductor region. 
     
     
         4 . The semiconductor structure recited in  claim 3  wherein the pads in each pair of the pads are disposed along parallel lines displaced from a line passing through the control electrode 
     
     
         5 . The semiconductor structure recited in  claim 1  wherein the compensation feature comprises a region in the control electrode on the inactive region wider than a region of the control electrode on the active semiconductor region and narrower than the contact pad for the control electrode. 
     
     
         6 . A method for forming a semiconductor structure, such structure having: a substrate; an active device formed in an active semiconductor region of the substrate, the active device having a control electrode for controlling a flow of carriers through the active semiconductor region between a pair of electrical contacts, the method comprising:
 forming a photoresist layer over the pair of contacts prior to formation of the gate electrode; and   providing a photolithographic, thickness non-uniformity, compensation feature prior to the forming of the photoresist layer, the feature being disposed on the surface substrate off of the active semiconductor region for preventing pooling of the photoresist layer on the active semiconducting region.   
     
     
         7 . The method recited in  claim 6  wherein the feature forming includes forming pads on the surface of the substrate and off of the active semiconductor region. 
     
     
         8 . A semiconductor structure, comprising:
 a substrate;   an active device formed in an active semiconductor region of the substrate, the active device having a control electrode for controlling a flow of carriers through the active semiconductor region, the control electrode extending from the active semiconductor region to a contact pad on the substrate off of the active semiconductor region. and wherein a portion of the control electrode between the active semiconductor region and the contact pad is wider than a portion of the control electrode on the active semiconductor region.   
     
     
         9 . A semiconductor structure, comprising:
 a substrate;   an active device formed in an active semiconductor region of the substrate, the active device having a control electrode for controlling a flow of carriers through the active semiconductor region between a pair of additional electrodes on the active semiconductor region, the control electrode extending from the active semiconductor region to a region on the substrate off of the active semiconductor region;   a pair of pads off of the active semiconductor region and adjacent to the pair of additional electrodes; and   wherein the portion of the control electrode off of the active semiconductor region is disposed between the pair of pads.   
     
     
         10 . The semiconductor structure recited in  claim 9  wherein a region of the control electrode off of the active semiconductor region is wider than a region of the control electrode on the active semiconductor region. 
     
     
         11 . A semiconductor structure, comprising:
 a substrate;   an active device formed in an active semiconductor region, the active device having a control electrode for controlling a flow of carriers through the active semiconductor region between a pair of electrical contacts on the active semiconductor region, wherein the pair of electrical contacts extend along parallel lines; and   two pair of pads off of the active semiconductor region, each pair of the two pair of pads being disposed along a corresponding one of the parallel lines.   
     
     
         12 . The semiconductor structure recited in  claim 11 , wherein the control electrode extends from the active semiconductor region to a region on the substrate off of the active semiconductor region; and wherein the control electrode off of the active semiconductor region is disposed between one of the two pair of pads. 
     
     
         13 . A semiconductor structure, comprising:
 a substrate;   an active device formed in an active semiconductor region of the substrate, the active device having a control electrode for controlling a flow of carriers through the active semiconductor region, the control electrode extending from a region on the active semiconductor region to a region on the substrate off of the active semiconductor region, the control electrode terminating in a contact pad on the substrate off of the active semiconductor region; and   wherein a region in the control electrode off of the active semiconductor region wider than a region of the control electrode on active semiconductor region and narrower than the contact pad for the control electrode.   
     
     
         14 . The semiconductor structure recited in  claim 13  including:
 a pair of additional electrodes on the active semiconductor region and wherein the control electrode controls the flow of carriers between the pair of additional electrode, and 
 two pair of pads the substrate off of the active semiconductor region and adjacent to the pair of additional electrodes; 
 wherein the pair of additional electrodes extend along parallel lines; 
 wherein each pair of the two pair of pads is disposed along a corresponding one of the parallel lines. 
 
     
     
         15 . The semiconductor structure recited in  claim 14 , wherein the control electrode extends from the active semiconductor region to a region on the substrate off of the active semiconductor region; and wherein the control electrode off of the active semiconductor region is disposed between the pair of pads. 
     
     
         16 . The semiconductor structure recited in  claim 14  wherein the control electrode is disposed along a line parallel to the aforementioned parallel lines and extends, at each opposing end of the control electrode, from the active semiconductor region to regions on the substrate off of the active semiconductor region; and wherein each opposing end of the control electrode is disposed between a corresponding one of the pair of pads. 
     
     
         17 . The semiconductor structure recited in  claim 2  wherein the pads are extensions of the pair of electrical conductors. 
     
     
         18 . The semiconductor structure recited in  claim 3  wherein the pads are extensions of the electrical conductors.