System and Method for Increasing Productivity of Combinatorial Screening

Abstract

The present invention provides systems and methods for simultaneous, parallel and/or rapid serial testing of material parameters or other parameters of the result of a process. The testing is typically used for screening different methods or materials to select those methods or materials with desired properties. A reactor structure used to form the materials may consist of an array of small isolated reaction chambers that overlie the substrate so that the substrate forms a bottom surface of each isolated reaction chamber. Test structures are formed on the substrate, where the location of each test structure corresponds to an isolated reaction chamber area of the reaction structure. Test structures are used to measure certain parameters, such as by probing contact pads for each test structure, or such testing may be performed in-situ during processing.

What is claimed is: 
     
         1 . A method for performing a process and testing the results of the process, the method comprising:
 aligning a semiconductor substrate with a reactor array, wherein the reactor array comprises a pattern of isolated reaction areas for performing a semiconductor process in each reaction area and openings with removable sleeves disposed therein, the reactor array being operable to form multiple layers of different materials in different isolated reaction areas without changing orientation of the reactor array, and wherein the semiconductor substrate forms a surface of the reaction areas and has a plurality of test structures fabricated thereon, each test structure comprising a structure that facilitates testing of at least one parameter of the results of the semiconductor process and at least some of the test structures having a location corresponding to a reaction area of the reactor array;   performing the semiconductor process in each of the reaction areas over the respective test structure with a respective process device of a plurality of process devices, each of the process devices forming a seal with a top surface of the respective removable sleeve, wherein a bottom surface of the removable sleeve seals with a top surface of the semiconductor substrate; and   communicating with the test structures to detect properties of the results of the semiconductor processes performed over the test structures.   
     
     
         2 . The method of  claim 1  wherein the semiconductor substrate and the reactor array are aligned with a support tray. 
     
     
         3 . The method of  claim 2  further comprising affixing the reactor array to the semiconductor substrate with the support tray after the aligning of the semiconductor substrate with the reactor array. 
     
     
         4 . The method of  claim 1  further comprising communicating with baseline test structures, formed in areas of the semiconductor substrate outside of the reaction areas that are unaffected by processing within the reaction areas, and comparing information provided by the baseline test structures to information obtained by the test structures within the reaction areas. 
     
     
         5 . The method of  claim 1  wherein the test structures in the reaction areas are all the same. 
     
     
         6 . The method of  claim 1  wherein the test structures in the reaction areas are not all the same and the test structures detect a variety of properties of the results of the semiconductor process. 
     
     
         7 . The method of  claim 1  wherein at least some of the test structures in the reaction areas test for electrical properties of the results of the semiconductor process. 
     
     
         8 . The method of  claim 1  wherein at least some of the test structures in the reaction areas test for non-electrical properties of the results of the semiconductor process. 
     
     
         9 . The method of  claim 1  wherein at least some of the test structures consist of physical test structures, chemical test structures, mechanical test structures, magnetic test structures, optical test structures, or electrical test structures. 
     
     
         10 . The method of  claim 1  wherein the semiconductor process performed in each reaction area comprises at least one of physical modifications, chemical modifications, electrical modifications, thermal modifications, magnetic modifications, photonic modifications, and photolytic modifications, and wherein the at least one of physical modifications, chemical modifications, electrical modifications, thermal modifications, magnetic modifications, photonic modifications, and photolytic modifications include at least one of cleaning, surface modification, surface preparation, deposition, etching, planarization, chemical mechanical planarization, electrochemical mechanical planarization, lithography, patterning, implantation, irradiation, electromagnetic irradiation, microwave irradiation, radio frequency (RF) irradiation, thermal treatment, infrared (IR) treatment, ultraviolet (UV) treatment, deep ultraviolet (DUV) treatment, extreme ultraviolet (EUV) treatment, electron beam treatment, and x-ray treatment. 
     
     
         11 . A method for performing a process and testing the results of the process, the method comprising:
 aligning a semiconductor substrate and a reactor array with a support tray, wherein the reactor array comprises a pattern of isolated reaction areas for performing a semiconductor process in each reaction area and openings with removable sleeves disposed therein, the reactor array being operable to form multiple layers of different materials in different isolated reaction areas without changing orientation of the reactor array, and wherein the semiconductor substrate forms a surface of the reaction areas and has a plurality of test structures fabricated thereon, each test structure comprising a structure that facilitates testing of at least one parameter of the results of the semiconductor process and at least some of the test structures having a location corresponding to a reaction area of the reactor array;   affixing the reactor array to the semiconductor substrate with the support tray after the aligning of the semiconductor substrate with the reactor array;   performing the semiconductor process in each of the reaction areas over the respective test structure with a respective process device of a plurality of process devices, each of the process devices forming a seal with a top surface of the respective removable sleeve, wherein a bottom surface of the removable sleeve seals with a top surface of the semiconductor substrate; and   communicating with the test structures to detect properties of the results of the semiconductor processes performed over the test structures.   
     
     
         12 . The method of  claim 11  further comprising communicating with baseline test structures, formed in areas of the semiconductor substrate outside of the reaction areas that are unaffected by processing within the reaction areas, and comparing information provided by the baseline test structures to information obtained by the test structures within the reaction areas. 
     
     
         13 . The method of  claim 12  wherein the semiconductor process performed in each reaction area comprises at least one of physical modifications, chemical modifications, electrical modifications, thermal modifications, magnetic modifications, photonic modifications, and photolytic modifications, and wherein the at least one of physical modifications, chemical modifications, electrical modifications, thermal modifications, magnetic modifications, photonic modifications, and photolytic modifications include at least one of cleaning, surface modification, surface preparation, deposition, etching, planarization, chemical mechanical planarization, electrochemical mechanical planarization, lithography, patterning, implantation, irradiation, electromagnetic irradiation, microwave irradiation, radio frequency (RF) irradiation, thermal treatment, infrared (IR) treatment, ultraviolet (UV) treatment, deep ultraviolet (DUV) treatment, extreme ultraviolet (EUV) treatment, electron beam treatment, and x-ray treatment. 
     
     
         14 . The method of  claim 11  wherein the semiconductor substrate is a first semiconductor substrate for a primary level of screening of the results of the processes performed in the reaction areas, and wherein the plurality of test structures comprises a plurality of primary level test structures for the primary level of screening, and further comprising:
 aligning a second semiconductor substrate with a second reactor array, a plurality of secondary level test structures being fabricated on the second semiconductor substrate for a secondary level of screening of the results of semiconductor processes performed in reaction areas in the second reactor array, at least some of the secondary level test structures having a location corresponding to a reaction area of the second reactor array, each secondary level test structure comprising a structure that facilitates testing of at least one parameter of the results of the semiconductor process performed over the secondary level test structures, the secondary level test structures being different from the primary level test structures and facilitating testing that is more complex than testing performed for the primary level of screening. 
 
     
     
         15 . The method of  claim 11  wherein communicating with the test structures comprises contacting probe pads formed on the semiconductor substrate, wherein the probe pads are connected to one or more test structures formed on the semiconductor substrate. 
     
     
         16 . A method for performing a process and testing the results of the process, the method comprising:
 aligning a semiconductor substrate and a reactor array with a support tray, wherein the reactor array comprises a pattern of isolated reaction areas for performing a semiconductor process in each reaction area and openings with removable sleeves disposed therein, the reactor array being operable to form multiple layers of different materials in different isolated reaction areas without changing orientation of the reactor array, and wherein the semiconductor substrate forms a surface of the reaction areas and has a plurality of test structures fabricated thereon, each test structure comprising a structure that facilitates testing of at least one parameter of the results of the semiconductor process and at least some of the test structures having a location corresponding to a reaction area of the reactor array;   affixing the reactor array to the semiconductor substrate with the support tray after the aligning of the semiconductor substrate with the reactor array;   performing the semiconductor process in each of the reaction areas over the respective test structure with a respective process device of a plurality of process devices, each of the process devices forming a seal with a top surface of the respective removable sleeve, wherein a bottom surface of the removable sleeve seals with a top surface of the semiconductor substrate; and   communicating with the test structures to detect properties of the results of the semiconductor processes performed over the test structures,   wherein the semiconductor process performed in each reaction area comprises at least one of physical modifications, chemical modifications, electrical modifications, thermal modifications, magnetic modifications, photonic modifications, and photolytic modifications, and wherein the at least one of physical modifications, chemical modifications, electrical modifications, thermal modifications, magnetic modifications, photonic modifications, and photolytic modifications include at least one of cleaning, surface modification, surface preparation, deposition, etching, planarization, chemical mechanical planarization, electrochemical mechanical planarization, lithography, patterning, implantation, irradiation, electromagnetic irradiation, microwave irradiation, radio frequency (RF) irradiation, thermal treatment, infrared (IR) treatment, ultraviolet (UV) treatment, deep ultraviolet (DUV) treatment, extreme ultraviolet (EUV) treatment, electron beam treatment, and x-ray treatment.   
     
     
         17 . The method of  claim 16  further comprising communicating with baseline test structures, formed in areas of the semiconductor substrate outside of the reaction areas that are unaffected by processing within the reaction areas, and comparing information provided by the baseline test structures to information obtained by the test structures within the reaction areas. 
     
     
         18 . The method of  claim 16  wherein the test structures in the reaction areas are all the same. 
     
     
         19 . The method of  claim 16  wherein the test structures in the reaction areas are not all the same and the test structures detect a variety of properties of the results of the semiconductor process. 
     
     
         20 . The method of  claim 16  wherein at least some of the test structures in the reaction areas test for electrical properties of the results of the semiconductor process.