Nonvolatile semiconductor memory device

Abstract

A nonvolatile semiconductor memory device comprises a plurality of memory blocks, each including a plurality of cell units and each configured as a unit of execution of an erase operation. Each of the cell units comprises a memory string, a first transistor, a second transistor, and a diode. The first transistor has one end connected to one end of the memory string. The second transistor is provided between the other end of the memory string and a second line. The diode is provided between the other end of the first transistor and a first line. The diode comprises a second semiconductor layer of a first conductivity type and a third semiconductor layer of a second conductivity type.

What is claimed is: 
     
         1 . A nonvolatile semiconductor memory device, comprising:
 a plurality of memory blocks, each including a plurality of cell units and each configured as a smallest unit of an erase operation;   a first line provided commonly to the plurality of memory blocks and connected to one ends of the plurality of cell units;   a second line connected to the other ends of the plurality of cell units; and   a control circuit configured to control a voltage applied to the plurality of memory blocks,   each of the plurality of cell units comprising:   a memory string configured by a plurality of memory transistors connected in series, the memory transistors being electrically rewritable;   a first transistor having one end connected to one end of the memory string;   a second transistor provided between the other end of the memory string and the second line; and   a diode provided between the first transistor and the first line and having a forward bias direction from a side of the first transistor to a side of the first line,   the memory string comprising:   a first semiconductor layer including a columnar portion extending in a perpendicular direction with respect to a substrate, the first semiconductor layer being configured to function as a body of the memory transistors;   a charge storage layer formed to surround a side surface of the columnar portion and configured to be capable of storing a charge; and   a first conductive layer formed commonly in the plurality of memory blocks to surround the side surface of the columnar portion with the charge storage layer interposed therebetween, the first conductive layer being configured to function as a gate of the memory transistors, and   the diode comprising:   a second semiconductor layer of a first conductivity type, the second semiconductor layer extending in the perpendicular direction with respect to the substrate; and   a third semiconductor layer of a second conductivity type, the third semiconductor layer being in contact with an upper surface of the second semiconductor layer and extending in the perpendicular direction with respect to the substrate,   the control circuit being configured to perform the erase operation in a selected one of the memory blocks by setting a voltage of the first line higher than a voltage of a gate of the first transistor by a first voltage to generate a GIDL current for raising a voltage of the body of the memory transistors, and setting a voltage of the gate of the memory transistors lower than the voltage of the body of the memory transistors by a second voltage, and   the control circuit being configured to prohibit the erase operation in an unselected one of the memory blocks by setting a voltage difference between the voltage of the first line and the voltage of the gate of the first transistor to a third voltage different from the first voltage for prohibiting generation of the GIDL current.