Delay Locked Loop

Abstract

A delay locked loop, comprises: a phase detector, wherein the phase detector generates output signals as a function of a reference clock signal and a feedback clock signal; a charge pump, wherein the charge pump generates a charge pump voltage as a function of the output signals; a bias generation circuit, wherein the bias generation circuit generates biasing signals as a function of the charge pump voltage; and a delay chain, wherein the delay chain outputs one or more internal clock signals and the feedback clock signal as a function of the reference clock signal and the biasing signals.

We claim: 
     
         1 . A delay locked loop, comprising:
 a phase detector, wherein the phase detector generates output signals as a function of a reference clock signal and a feedback clock signal;   a charge pump, wherein the charge pump generates a charge pump voltage as a function of the output signals;   a bias generation circuit, wherein the bias generation circuit generates biasing signals as a function of the charge pump voltage; and   a delay chain, wherein the delay chain outputs one or more internal clock signals and the feedback clock signal as a function of the reference clock signal and the biasing signals.   
     
     
         2 . The delay locked loop of  claim 1  wherein the charge pump comprises a first self-biased amplifier (“OTA 1 ”), a second self-biased amplifier (“OTA 2 ”), and transistors. 
     
     
         3 . The delay locked loop of  claim 2  wherein a first transistor, a second transistor, a third transistor, and a fourth transistor of the transistors are serially connected transistors, and wherein the OTA 1  and the serially connected transistors are connected together to provide a dummy load for the charge pump. 
     
     
         4 . The delay locked loop of  claim 3   wherein the source of the first transistor is connected to a first voltage,   wherein the drain of the first transistor and the source of the second transistor are connected together,   wherein the drain of the second transistor, the drain of the third transistor, and the negative input of the OTA 1  are connected together,   wherein the source of the third transistor is connected to the drain of the fourth transistor,   wherein the source of the fourth transistor is connected to a second voltage,   wherein the positive output of the OTA 1  is applied to the gate of the first transistor,   wherein the second voltage is applied to the gate of the second transistor,   wherein the first voltage is applied to the gate of the third transistor,   wherein the negative output of the OTA 1  is applied to the gate of the fourth transistor, and   wherein the charge pump voltage is applied to the positive input of the OTA 1 .   
     
     
         5 . The delay locked loop of  claim 2  wherein the OTA 2  is connected in a negative feedback loop to adjust the charge pump voltage as a function of the output signals from the phase detector. 
     
     
         6 . The delay locked loop of  claim 5   wherein a fifth transistor and a sixth transistor of the transistors are connected in series,   wherein a seventh transistor and an eighth transistor of the transistors are connected in series,   wherein the sources of the fifth and seventh transistors are connected together,   wherein the drains of the sixth and eighth transistors are connected together,   wherein the drains of the fifth and sixth transistors and the positive input of the OTA 2  are connected together,   wherein the drains of the seventh and eighth transistors, the output of the OTA 2 , and the negative input of the OTA 2  are connected together to generate the charge pump voltage, and   wherein the gates of the fifth, sixth, seventh, and eighth transistors are controlled by the output signals of the phase detector.   
     
     
         7 . The delay locked loop of  claim 6   wherein the charge pump further comprises a first switch and a second switch,   wherein the positive output of the OTA 1  is connected to the gate of a ninth transistor of the transistors,   wherein the positive output of the OTA 1  is connected to the gate of a tenth transistor of the transistors via the first switch,   wherein the negative output of the OTA 1  is connected to the gate of a eleventh transistor of the transistors,   wherein the negative output of the OTA 1  is connected to the gate of a twelfth transistor of the transistors via the second switch,   wherein the sources of the ninth transistor and the tenth transistor are connected to a first voltage,   wherein the drains of the ninth transistor and the tenth transistor are connected to the sources of the fifth and seventh transistors,   wherein the sources of the eleventh transistor and the twelfth transistor are connected to a second voltage, and   wherein the drains of the eleventh transistor and the twelfth transistor are connected to the sources of the sixth and eighth transistors.   
     
     
         8 . The delay locked loop of  claim 1  further comprising an initialization circuit for providing a pulse generation signal for the charge pump voltage during initialization of the delay locked loop. 
     
     
         9 . The delay locked loop of  claim 1  further comprising a loop capacitor, wherein the loop capacitor is connected to the charge pump voltage to filter out noise from the charge pump voltage. 
     
     
         10 . A delay locked loop, comprising:
 a phase detector, wherein the phase detector generates output signals as a function of a reference clock signal and a feedback clock signal;   a charge pump, wherein the charge pump generates a charge pump voltage as a function of the output signals and wherein the charge pump comprises a first self-biased amplifier (“OTA 1 ”), a second self-biased amplifier (“OTA 2 ”), and transistors;   a bias generation circuit, wherein the bias generation circuit generates biasing signals as a function of the charge pump voltage; and   a delay chain, wherein the delay chain outputs one or more internal clock signals and the feedback clock signal as a function of the reference clock signal and the biasing signals, and wherein the OTA 2  is connected in a negative feedback loop to adjust the charge pump voltage as a function of the output signals from the phase detector.   
     
     
         11 . The delay locked loop of  claim 10  wherein a first transistor, a second transistor, a third transistor, and a fourth transistor of the transistors are serially connected transistors, and wherein the OTA 1  and the serially connected transistors are connected together to provide a dummy load for the charge pump. 
     
     
         12 . The delay locked loop of  claim 11   wherein the source of the first transistor is connected to a first voltage,   wherein the drain of the first transistor and the source of the second transistor are connected together,   wherein the drain of the second transistor, the drain of the third transistor, and the negative input of the OTA 1  are connected together,   wherein the source of the third transistor is connected to the drain of the fourth transistor,   wherein the source of the fourth transistor is connected to a second voltage,   wherein the positive output of the OTA 1  is applied to the gate of the first transistor,   wherein the second voltage is applied to the gate of the second transistor,   wherein the first voltage is applied to the gate of the third transistor,   wherein the negative output of the OTA 1  is applied to the gate of the fourth transistor, and   wherein the charge pump voltage is applied to the positive input of the OTA 1 .   
     
     
         13 . The delay locked loop of  claim 10   wherein a fifth transistor and a sixth transistor of the transistors are connected in series,   wherein a seventh transistor and an eighth transistor of the transistors are connected in series,   wherein the sources of the fifth and seventh transistors are connected together,   wherein the drains of the sixth and eighth transistors are connected together,   wherein the drains of the fifth and sixth transistors and the positive input of the OTA 2  are connected together,   wherein the drains of the seventh and eighth transistors, the output of the OTA 2 , and the negative input of the OTA 2  are connected together to generate the charge pump voltage, and   wherein the gates of the fifth, sixth, seventh, and eighth transistors are controlled by the output signals of the phase detector.   
     
     
         14 . The delay locked loop of  claim 13   wherein the charge pump further comprises a first switch and a second switch,   wherein the positive output of the OTA 1  is connected to the gate of a ninth transistor of the transistors,   wherein the positive output of the OTA 1  is connected to the gate of a tenth transistor of the transistors via the first switch,   wherein the negative output of the OTA 1  is connected to the gate of a eleventh transistor of the transistors,   wherein the negative output of the OTA 1  is connected to the gate of a twelfth transistor of the transistors via the second switch,   wherein the sources of the ninth transistor and the tenth transistor are connected to a first voltage,   wherein the drains of the ninth transistor and the tenth transistor are connected to the sources of the fifth and seventh transistors,   wherein the sources of the eleventh transistor and the twelfth transistor are connected to a second voltage, and   wherein the drains of the eleventh transistor and the twelfth transistor are connected to the sources of the sixth and eighth transistors.   
     
     
         15 . The delay locked loop of  claim 10  further comprising an initialization circuit for providing a pulse generation signal for the charge pump voltage during initialization of the delay locked loop. 
     
     
         16 . The delay locked loop of  claim 10  further comprising a loop capacitor, wherein the loop capacitor is connected to the charge pump voltage to filter out noise from the charge pump voltage. 
     
     
         17 . A delay locked loop, comprising:
 a phase detector, wherein the phase detector generates output signals as a function of a reference clock signal and a feedback clock signal;   a charge pump, wherein the charge pump generates a charge pump voltage as a function of the output signals and wherein the charge pump comprises a first self-biased amplifier (“OTA 1 ”), a second self-biased amplifier (“OTA 2 ”), and transistors;   a loop capacitor, wherein the loop capacitor is connected to the charge pump voltage to filter out noise from the charge pump voltage;   an initialization circuit for providing a pulse generation signal for the charge pump voltage during initialization of the delay locked loop;   a bias generation circuit, wherein the bias generation circuit generates biasing signals as a function of the charge pump voltage; and   a delay chain,   wherein the delay chain outputs one or more internal clock signals and the feedback clock signal as a function of the reference clock signal and the biasing signals,   wherein a first transistor, a second transistor, a third transistor, and a fourth transistor of the transistors are serially connected transistors,   wherein the OTA 1  and the serially connected transistors are connected together to provide a dummy load for the charge pump, and   wherein the OTA 2  is connected in a negative feedback loop to adjust the charge pump voltage as a function of the output signals from the phase detector.   
     
     
         18 . The delay locked loop of  claim 17   wherein the source of the first transistor is connected to a first voltage,   wherein the drain of the first transistor and the source of the second transistor are connected together,   wherein the drain of the second transistor, the drain of the third transistor, and the negative input of the OTA 1  are connected together,   wherein the source of the third transistor is connected to the drain of the fourth transistor,   wherein the source of the fourth transistor is connected to a second voltage,   wherein the positive output of the OTA 1  is applied to the gate of the first transistor,   wherein the second voltage is applied to the gate of the second transistor,   wherein the first voltage is applied to the gate of the third transistor,   wherein the negative output of the OTA 1  is applied to the gate of the fourth transistor, and   wherein the charge pump voltage is applied to the positive input of the OTA 1 .   
     
     
         19 . The delay locked loop of  claim 17   wherein a fifth transistor and a sixth transistor of the transistors are connected in series,   wherein a seventh transistor and an eighth transistor of the transistors are connected in series,   wherein the sources of the fifth and seventh transistors are connected together,   wherein the drains of the sixth and eighth transistors are connected together,   wherein the drains of the fifth and sixth transistors and the positive input of the OTA 2  are connected together,   wherein the drains of the seventh and eighth transistors, the output of the OTA 2 , and the negative input of the OTA 2  are connected together to generate the charge pump voltage, and   wherein the gates of the fifth, sixth, seventh, and eighth transistors are controlled by the output signals of the phase detector.   
     
     
         20 . The delay locked loop of  claim 19   wherein the charge pump further comprises a first switch and a second switch,   wherein the positive output of the OTA 1  is connected to the gate of a ninth transistor of the transistors,   wherein the positive output of the OTA 1  is connected to the gate of a tenth transistor of the transistors via the first switch,   wherein the negative output of the OTA 1  is connected to the gate of a eleventh transistor of the transistors,   wherein the negative output of the OTA 1  is connected to the gate of a twelfth transistor of the transistors via the second switch,   wherein the sources of the ninth transistor and the tenth transistor are connected to a first voltage,   wherein the drains of the ninth transistor and the tenth transistor are connected to the sources of the fifth and seventh transistors,   wherein the sources of the eleventh transistor and the twelfth transistor are connected to a second voltage, and   wherein the drains of the eleventh transistor and the twelfth transistor are connected to the sources of the sixth and eighth transistors.